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Importing verilog to Cadence schematic

Hello,

I am trying to import a very simple verilog code containing one latch into Cadence using Import -> Verilog on CIW. I get the following error message.

INFO (VERILOGIN_GUI-13): Verilog Import process has started ...
ERROR (VERILOGIN-205): An internal memory error has occurred. Exiting.
INFO (VERILOGIN_GUI-15): Verilog Import completed. Look at logfile, ./verilogIn.log, for process execution details.

There is nothing in the logfile and I have enough memory. I am using IC6.1.5. Any help is appreciated!

Wonyoung

Quek over 13 years ago

Hi Wonyoung

Would you please try the following and see if it helps?

a. In "Import-Verilog" form, go to "Schematic Generation Options" tab
b. Disable "Full Place and Route" option which is located at the bottom of the form

If it does not help, please file a service request with your local Cadence support.

Best regards
Quek
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Wonyoung over 13 years ago

Hi Quek,
I just tried that but the problem is still there. Let me know if you have any other suggestions!
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Quek over 13 years ago

Hi Wonyoung

Would you please file a service request to your local Cadence support so that we can investigate this properly?

Thanks
Quek
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Wonyoung over 13 years ago

Hi Quek,

I will check with our university's IT people since they have the ID/password/license# required to login to the support site. Thanks!
Wonyoung
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Wonyoung over 13 years ago

Hi Quek,
I just submitted a service request in the Cadence support website. Thanks!
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Wonyoung over 13 years ago

At the same time, I am trying to see if using "verilog2oa" and "conn2sch" can import verilog to Cadence schematic using the following commands.
verilog2oa -verilog "./myverilog.syn.v" -top "myverilog" -lib "test" -view "netlist" -tieHigh VDD -tieLow VSS -overwrite

conn2sch -lib test -cell myverilog -view netlist -destlib test -destview schematic -verbose -param conn2sch.conf

When I run conn2sch, it complains that "ERROR (CONN2SCH-193): Instance XXX is not bound to any master.". I was wondering if you have any recommendations on how to fix this, and if you think using verilog2oa and conn2sch could be an alternative to importing verilog in CIW. Thank you very much!
Wonyoung
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Andrew Beckett over 13 years ago

I wouldn't recommend using verilog2oa - maybe you could use "ihdl" instead, but that's effectively the same command being used from the Import Verilog command.
Andrew.
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Quek over 13 years ago

Hi Wonyoung

Sorry that I cannot comment on "verilog2oa" because I don't use it myself. I do use the reverse cmd "oa2verilog" in my script and it works well. : )

Best regards
Quek
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Wonyoung over 13 years ago

Hi all,
I contacted customer support and they were very helpful in fixing the problem. There was a problem in my $path that was pointing to an old IC5 path instead of the IC6 that I was using. Thank you very much!
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weebey over 13 years ago

I am having this same exact problem, but can't seem to fix it. Anyone have some thoughts? Thanks.
I am running version IC6.1.5-64b-500.3
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