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Errors in ASSURA -- Cannot understand them

Thodoros

 Hello,

I tried to design several layouts in vortuoso with the umc 90nm technology and always after correcting a few others I

end up with the same collection of errors. These are:

1. Rule No. 856 : Design_guideline2: NWEL overlap PFET diffusion edge is recommended to be not less than 0.5um

However the PFET is automatically generated so I do not think that I have to change its NWEL boundary distance to the diffusion

 

2. Rule No. 853 : 4.1.13F_DFM.Priority5: Minimum extension of an DIFF region beyond a CONT region is 0.06um

Again the FET that includes the DIFF region and the CONT is automatically generated

3. Rule No. 842 : 4.2.1.1D.b1b2_DFM.Priority4: Minimum ME1 line end enclosure of CONT at ME1 outer corner is 0.06um,  Minimum ME1 line end enclosure of CONT for four sides is 0.02um,  Minimum ME1 line end enclosure of CONT is 0.06um

 These distances are also generated automatically

4. Rule No. 818 : 6A.ME1_NSR: Die corner rule 1, ME1 must draw with 135 angle

5.  Rule No. 709 : 5.1.ME1: Die seal ring rule 1, metal-1 must make a turn with 135 angle within regions 150um away from die corners.

6.  Rule No. 707 : 5.1.DIFF: Die seal ring rule 1, diffusion must make a turn with 135 angle within regions 150um away from die corners.

7. The Metal1 coverage must be larger than 20% over local 100um * 100um area step 50um

Same error for Metal 2,3,4,5,6 and 7

8. Rule No. 371 : 4.1.1G.a: Minimum diffusion density over 150umX150um area, stepping 50um is 25%.

 

What can I do to overcome these errors?

 

Moreover, I tried to run umc90nm_loadProcess() in the CIW, but instead of the Load Metal Option form,
I get the following error:

*Error* fprintf: argument #1 should be an I/O port (type template = "ptg") - nil

 

How does this affect me?

 

Thanks in Advance for your help,

Thodoros

  • Quek

    Hi Thodoros

    Actually it is possible for pcells to also have drc errors even though theoretically they should be drc clean. Sometimes small errors do slip through the QA process. For rules 1,2 and 3, if it is flagged on a pcell, then I think it would be better to report this to umc.

    For the rest of the rules, you can download the DRM (Design Rule Manual) from umc website for a complete description of the rules.

    Rule 7 means that if you divide your layout into 50x50um squares, the density of each square should be at least 20%. E.g. in any 50x50um square, area of all M1 divided by 50x50 must be at least 20%. Similar explanation applies for rule 8.

    I suspect that you might need start Virtuoso in the pdk directory itself instead of the working directory in order to do the metal option setup. There might be a hidden repository directory that is referenced by the script.

    Since your questions are mostly very specific to umc pdks, it would be better if you can contact ucm customer support about this. : )

    Best regards
    Quek

  • Thodoros

     Dear Quek,

    Thanks for your quick reply. I am trying to communicate with umc for these assura errors as in our fdk installation there are not any DRM manuals present.

    I am just wondering: Since I also tried to verify a simple inverter who's area is much smaller than 50umx50um why does that rule 7 issues? (And so does rule 4 and 5 which relates to metal-1 and diffusion turns with 135 angle).
    I do not want to verify a die, I just want to create an error free layout block or macro.

    Would it be a problem if I erase out those error checks that are issued?

    Is it possible instead of verifying a die, to set the tool to verify a block or standard cell so that those areas would be muck smaller??(Perhaps via avParameters. I have tried to verify a smaller area through Assura -> Run DRC -> Area to be checked -> Specify Area but the errors where the same)

     

    Thanks for your concern,

    Best regards,

    Thodoros
  • Quek

    Hi Thodoros

    I think there is most probably a switch in your drc rule deck that controls the set of rules for die-level or block-level verification. Would you please confirm if there is such a switch? Specifying a smaller checking area would most probably not help because the same rules are still being ran.

     
    Best regards
    Quek

  • Thodoros

     Hi Queck,

    You are right. There are a lot of switches at the drc rule deck and I am trying to use them as to bypass the die-level verification.

     Thanks for all the help,

    Thodoros

  • RAO VINAY

    Hello Thondors,

    I am also getting the same errors for UMC 90nm technology. I started with the simple inverter layout but end up in getting these errors. How can i resolve this? Your suggestion would be highly appreciated. Thank you. 

     

    Regards,

    Vinay Rao.

     

  • Thodoros

     Dear Vinay Rao,

     

    Sorry for my late response, but I was away from my office.

    What I do to overcome these assura error messages, is to select several assura drc switches. Mostly those that are related to density and die check.

     Regards,

    Thodoros.

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