Errors in ASSURA -- Cannot understand them

 Hello,

I tried to design several layouts in vortuoso with the umc 90nm technology and always after correcting a few others I

end up with the same collection of errors. These are:

1. Rule No. 856 : Design_guideline2: NWEL overlap PFET diffusion edge is recommended to be not less than 0.5um

However the PFET is automatically generated so I do not think that I have to change its NWEL boundary distance to the diffusion

 

2. Rule No. 853 : 4.1.13F_DFM.Priority5: Minimum extension of an DIFF region beyond a CONT region is 0.06um

Again the FET that includes the DIFF region and the CONT is automatically generated

3. Rule No. 842 : 4.2.1.1D.b1b2_DFM.Priority4: Minimum ME1 line end enclosure of CONT at ME1 outer corner is 0.06um,  Minimum ME1 line end enclosure of CONT for four sides is 0.02um,  Minimum ME1 line end enclosure of CONT is 0.06um

 These distances are also generated automatically

4. Rule No. 818 : 6A.ME1_NSR: Die corner rule 1, ME1 must draw with 135 angle

5.  Rule No. 709 : 5.1.ME1: Die seal ring rule 1, metal-1 must make a turn with 135 angle within regions 150um away from die corners.

6.  Rule No. 707 : 5.1.DIFF: Die seal ring rule 1, diffusion must make a turn with 135 angle within regions 150um away from die corners.

7. The Metal1 coverage must be larger than 20% over local 100um * 100um area step 50um

Same error for Metal 2,3,4,5,6 and 7

8. Rule No. 371 : 4.1.1G.a: Minimum diffusion density over 150umX150um area, stepping 50um is 25%.

What can I do to overcome these errors?

Moreover, I tried to run umc90nm_loadProcess() in the CIW, but instead of the Load Metal Option form,
I get the following error:

*Error* fprintf: argument #1 should be an I/O port (type template = "ptg") - nil

How does this affect me?

Thanks in Advance for your help,

Thodoros