spectre.dc saves array lines as out_0 not out<0>

Yayla,

If you're getting spectre to save out the node voltages etc into a file, it's only reasonable that it should do so using the names in the netlist. That way it can also read them back in with the readns option for DC.

I cannot understand what problem this would cause. You say that "Cadence couldn't figure out those wires and gives unknown net warning". Well, "Cadence" is a company name, not a tool - so which tool is complaining, and what are you doing?

The vector nets in the schematic will end up as a set of single nets in the spectre netlist, as the spectre language doesn't have the concept of buses. The simulator will then be able to read and write files (with "write" and "readns" or "readic") with no problem. I'm not sure of anything else that would be trying to read these files back into Virtuoso and might consequently expect to do some kind of mapping.

So please clarify your question/problem.

Thanks,

Andrew.

 Hi Andrew.

Thanks for reply. Let me restate my problem. We are using two models for Spectre Simulations: one from TSMC and one from UMC. When I am running simulation using TSMC model, there is no problem with convergence in transient and dc. However, when I try to run Spectre with UMC model, DC convergence fails. I tried to use TSMC initial conditions for UMC simulations. First, I have tried to use intial conditions that I have received from one of my colleague and in that one, busses are saved using "<>" not underscore. When I use this initial condition in Spectre with UMC model, I could start the simulation. However, when I have tried to generate my own initial conditions, it uses underscore for buses. Hence, Spectre gives unkown wire name warnings and Spectre has no convergence.

 I don't know why but yesterday I have closed my Cadence session and restart Cadence again. Then, it starts to save spectre.dc with "<>" in Spectre. I have used same Spectre state and Virtuoso Schematic. Although there is no problem with right now, I don't know how it was resolved.

Regards,

yayla

Ok, well there's a lot of information there that you didn't provide originally. Also, you didn't say which version of the tools you're using. It's quite possible that there's something in one of the PDK setups that is altering how the mapping is done when netlisting, and this is different between the two PDKs. In fact that's pretty much the only explanation as to why you might be getting different mapping in the two different cases.

Andrew.

I am using Cadence Virtuoso Spectre Circuit Simulator Version 10.1.1.200. The issue is that I am still using TSMC setup in Spectre to generate initial conditions as it was before. There is no change in the way I am generating spectre.dc but before I had the underscore issue but now everything seems OK. BTW, how can I learn Cadence Version from CIW?

 Thanks,

Mustafa

The simulator version isn't relevant here - it's the Virtuoso version, because it's that which is creating the netlist. The simulator is just consuming the netlist and will use whatever names have ended up in the netlist.

Help->About in the CIW will tell you the version/subversion information, or you could type getVersion(t) in the CIW.

That said, I'm not sure what help I'll be able to give since this is almost certainly PDK specific if you were using the same software versions in both cases.

Andrew.

Thanks Tawna. It is IC5.10.41.

Andrew,

I know that the problem is not so clear but again thanks for your help. As I said before, there is no problem now for spectre.dc.

Regards,

Mustafa