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spectre.dc saves array lines as out_0 not out<0>

yayla

 Hi,

I tried to save final value using "write" box in DC Options. I am saving spectre.dc file and trying to use it for next simulation but I have noticed that when I want to save buses like out<3:0>, it saves out_0, out_1 ... not out<0> or out<1> so that Cadence couldn't figure out those wires and gives unknown net warning. When I have changed those buses to <>, I can run the simulation. Do you know how to save spectre.dc as out<1> rather than out_1.

 

Thanks,

yayla
Parents

  •  Hi Andrew.

    Thanks for reply. Let me restate my problem. We are using two models for Spectre Simulations: one from TSMC and one from UMC. When I am running simulation using TSMC model, there is no problem with convergence in transient and dc. However, when I try to run Spectre with UMC model, DC convergence fails. I tried to use TSMC initial conditions for UMC simulations. First, I have tried to use intial conditions that I have received from one of my colleague and in that one, busses are saved using "<>" not underscore. When I use this initial condition in Spectre with UMC model, I could start the simulation. However, when I have tried to generate my own initial conditions, it uses underscore for buses. Hence, Spectre gives unkown wire name warnings and Spectre has no convergence.

     I don't know why but yesterday I have closed my Cadence session and restart Cadence again. Then, it starts to save spectre.dc with "<>" in Spectre. I have used same Spectre state and Virtuoso Schematic. Although there is no problem with right now, I don't know how it was resolved.

     

    Regards,

    yayla

     

Reply

  •  Hi Andrew.

    Thanks for reply. Let me restate my problem. We are using two models for Spectre Simulations: one from TSMC and one from UMC. When I am running simulation using TSMC model, there is no problem with convergence in transient and dc. However, when I try to run Spectre with UMC model, DC convergence fails. I tried to use TSMC initial conditions for UMC simulations. First, I have tried to use intial conditions that I have received from one of my colleague and in that one, busses are saved using "<>" not underscore. When I use this initial condition in Spectre with UMC model, I could start the simulation. However, when I have tried to generate my own initial conditions, it uses underscore for buses. Hence, Spectre gives unkown wire name warnings and Spectre has no convergence.

     I don't know why but yesterday I have closed my Cadence session and restart Cadence again. Then, it starts to save spectre.dc with "<>" in Spectre. I have used same Spectre state and Virtuoso Schematic. Although there is no problem with right now, I don't know how it was resolved.

     

    Regards,

    yayla

     

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