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IBM_PDK 7RF, IC6.14, Extraction of circuit

Kabal

Do i need to use Assura4.1 for extraction? Or it is only for LVS and DRC?

Usually in an old IC5.141 we just clicked Verify->Extract, and then there was extract rule, i beleive from Diva, so thats how it worked.

 

How to extract a layout in IC6.14 with Assura4.1 installed? 

 I already succeeded in schematics of simple inverter and its simulation with spectre (MMSIM10). Now im just trying to extract basic nmos and pmos layed out in Layout XL.

 

In my kit, i see extract4,5,6,7.rul files. But none of them are recognized by the tool. so i believe things must be done in a different way, any ideas abouot that?

 

thank you.

Parents

  • You'd be better off asking this to IBM or your technology provider. As far as I remember you should check the following...

    - After generating the cdl netlist there is a cdl preprocessor for lvs which produces a cellname.netlist.lvs which you use as the schematic design source

    - Did you copy assura_tech.lib to your working directory?

Reply

  • You'd be better off asking this to IBM or your technology provider. As far as I remember you should check the following...

    - After generating the cdl netlist there is a cdl preprocessor for lvs which produces a cellname.netlist.lvs which you use as the schematic design source

    - Did you copy assura_tech.lib to your working directory?

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