IBM_PDK 7RF, IC6.14, Extraction of circuit

The Verify->Extract approach you were talking about was indeed Diva. 

It depends on the PDK (and I don't know the details for the specific PDK you're using - you would be best asking the provider of the PDK - presumably IBM), but it appears that the extractN.rul files you are talking about are the rules needed for the extraction part of LVS for Assura. I suspect that the number refers to the top metal layer, so depends on which metal stack you're using, maybe. This extraction is to take care of the designed devices (not parasitics).

Once you have it LVS'd, you should be able to run QRC (formerly this would have been Assura RCX, but that is obsolete now) starting from the LVS results. This will extract the parasitics you want. I would imagine the PDK has some documentation telling you the expected flow - so I'd start from there, and if not contact IBM or whoever you got it from. Sometimes there are folks from IBM on this forum, or you may find somebody familiar with the particular PDK you're referring to who can give more specific advice.

Regards,

Andrew.

An overview of the tools compatible with the 7RF PDK (and other IBM PDKs offered by MOSIS) can be found here:

http://www.mosis.com/vendors/view/ibm/design-kit-cmos

 Ok, here is what i have now:

1) in schematic i choose, IBM_PDK->Netlist->Create CDL Netlist,  then inv.netlist file is created successfully.

 2) Once i specified all the rule files in Assura LVS, as well as Schematic Design Source: Netlist, and then choose inv.netlist file extracted from schematic.  I then run it, but it gives me a huge log files with lots of errors like it doesnt recognize specific device.

so from my understanding, it doesnt know whats going on. Another thing which kind of doenst look right is: when i run LVS Assura, and window opens, on the Technology it shows: undefined,...

also, in the LVS avParameters Setup i see same thing: Technology: undefined.    How do i fix that? or do i need to?

or what other things must be turned/tweaked in Assura to be able to work with any technology?

You'd be better off asking this to IBM or your technology provider. As far as I remember you should check the following...

- After generating the cdl netlist there is a cdl preprocessor for lvs which produces a cellname.netlist.lvs which you use as the schematic design source

- Did you copy assura_tech.lib to your working directory?

 Thanks, that was a catch too. Once i copied assura_tech.lib file i could choose my technology.

 Another thing i was doing wrong is, pointing LVS to compare/bind rules with .vldb extension, i had to point it to .cdl extension.

 Also, i had to add substrate contact in schematic.

 After that it LVSed fine.