• Skip to main content
  • Skip to search
  • Skip to footer
Cadence Home
  • This search text may be transcribed, used, stored, or accessed by our third-party service providers per our Cookie Policy and Privacy Policy.

  1. Community Forums
  2. Custom IC Design
  3. Error during ASSURA parasitic extraction.

Stats

  • Locked Locked
  • Replies 1
  • Subscribers 126
  • Views 13194
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

Error during ASSURA parasitic extraction.

RAO VINAY
RAO VINAY over 13 years ago
 Hello all,

I am using assura 3.1.6 USR 1 with IC 5141 hotfix and also with UMC 90nm technology. DRC (by setting some switches) and LVS ran successfully for my simple inverter layout but RCX gave the following error.

capgen Capgen results will be written to directory: /home/vinay_rao/work/test2

*ERROR* at "capgen": -blocking mask layer 'NCAPGATE_25' not defined in LVS filequitting.

Forking:/cad/cadence/ASSURA316/tools/assura/bin/32bit/capgen-techdir /home/vinay_rao/work/foundry/umc90/RuleDecks/Assura/LVS/../LPE/Option13 -lvs /home/vinay_rao/work/test2.xcn -p2lvs /home/vinay_rao/work/foundry/umc90/RuleDecks/Assura/LVS/../LPE/Option13/p2lvsfile -sw3d -add_via_effect me1,dif -blocking RFSYMBOL,sub,dif,ply,me1,me2,me3,me4,me5,me6,me7,me8,me9,alrdl -res_blocking RFSYMBOL,PLY,M1,M2,M3,M4,M5,M6,M7,M8,M9,AL_RDL -blocking NCAPGATE_10,ply,dif,sub -blocking NCAPGATE_12,ply,dif,sub -blocking NCAPGATE_25,ply,dif,sub -blocking NCAPGATE_HVT_10,ply,dif,sub -blocking NCAPGATE_HVT_12,ply,dif,sub -blocking NCAPGATE_N_25,ply,dif,sub -length_units meters -p ply,Allgates,dif -cap_unit 1 /home/vinay_rao/work/test2

*WARNING* Bad return status from RCX script generator. 0x100


I also went through the post http://www.cadence.com/forums/p/13908/22563.aspx which has got the same error but I didn’t find ‘resimulate_extracted’ switch set (as it is foundry dependent). And I didn’t understand clearly about Quek reply.

Can anyone suggest me how to resolve this for UMC files?

Regards,

Vinay Rao.
  • Cancel
Parents
  • Quek
    Quek over 13 years ago

    Hi Vinay Rao

    To put it simply, the Assura LVS extract.rul file which you are using is out-of-sync with the contents of the QRC tech directory. There might have been some layer changes which are not reflected in the QRC setup files. You can download the latest version of the pdk and retry. If it still results in error, you will need to report this to the foundry. : )

    Best regards
    Quek

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Reply
  • Quek
    Quek over 13 years ago

    Hi Vinay Rao

    To put it simply, the Assura LVS extract.rul file which you are using is out-of-sync with the contents of the QRC tech directory. There might have been some layer changes which are not reflected in the QRC setup files. You can download the latest version of the pdk and retry. If it still results in error, you will need to report this to the foundry. : )

    Best regards
    Quek

    • Cancel
    • Vote Up 0 Vote Down
    • Cancel
Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.

© 2025 Cadence Design Systems, Inc. All Rights Reserved.

  • Terms of Use
  • Privacy
  • Cookie Policy
  • US Trademarks
  • Do Not Sell or Share My Personal Information