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analog-mixed signal simulation with verilog-a vhdl and circuit components

Zitty

 Hello,

 I´m working on a mixed signal circuit with several circuit compnents on transistor level and some digial compnents in vhdl. The latter will be transferred into a digital layout with standard cells.

 My hole test surrounding conatins components programmed in veriloga.

 To start I used also veriloga code for the digital components. So it was possible to use the normal spectre simulator.

Circuits with only transistorlevel components and vhdl components were simulated using the ams-simulator and that worked fine for me.But  I could not simulate circuits including the veriloga code this way.

Is there a possibility to simulate a circuit containing transistor level components, veriloa code and vhdl components? Or do I have to transfer all my veriloga components into vhdl? the problem is that mixed signal simulation takes quite long.

 

thanks

Parents

  •  yes i meant the hierachchy editor. and no i dit not have the verilog a switch on. i think that was the first problem.

     

    i´m using cadence virtuoso 6.1.5. how can i find out which version of the ams simulator i´m currently using?

     i´m getting another error message now, which was not shown before.

    it says:

    file: /soft64/Cadence/IUS_81U1/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/R2E/module/verilog.vams
    ncvlog: *E,DLPAKW: Attempt to write module connectLib.R2E:module (VST) into a read-only library.
        module connectLib.R2E:module
            errors: 1, warnings: 0
        Total errors/warnings found outside modules and primitives:
            errors: 0, warnings: 1
    ncvlog: Memory Usage - 11.1M program + 8.2M data = 19.2M total
    ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 89.6% cpu)
    Failed to compile ('connectLib' 'R2E' 'module').
    Compilation failed.
    Successfully compiled: 0
    Failed to compile: 1

Reply

  •  yes i meant the hierachchy editor. and no i dit not have the verilog a switch on. i think that was the first problem.

     

    i´m using cadence virtuoso 6.1.5. how can i find out which version of the ams simulator i´m currently using?

     i´m getting another error message now, which was not shown before.

    it says:

    file: /soft64/Cadence/IUS_81U1/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/R2E/module/verilog.vams
    ncvlog: *E,DLPAKW: Attempt to write module connectLib.R2E:module (VST) into a read-only library.
        module connectLib.R2E:module
            errors: 1, warnings: 0
        Total errors/warnings found outside modules and primitives:
            errors: 0, warnings: 1
    ncvlog: Memory Usage - 11.1M program + 8.2M data = 19.2M total
    ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.0s, 89.6% cpu)
    Failed to compile ('connectLib' 'R2E' 'module').
    Compilation failed.
    Successfully compiled: 0
    Failed to compile: 1

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