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VHDL-AMS complie error

sr1857

 Dear All,

I am trying to create a testbench that includes a transducer written in VHDL-AMS and some standard components from analogLib. When I try to 'Netlist and run' a transient solution I get the following error. Could anybodypoint me in the right direction?

Many thanks,

Sunil.

file: /usr/local/cds-een/cadence/ius/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/ConnRules_18V_basic/connect/verilog.vams
ncvlog: *E,DLPAKW: Attempt to write connect connectLib.ConnRules_18V_full_fast:connect (VST) into a read-only library.
    connect connectLib.ConnRules_18V_full_fast:connect

 

Parents

  • Sunil,

    How are  you running the simulation? Is it from the Hierarchy Editor AMS Plugin? Is it from the Analog Design Environment (with ams as the simulator)? If in ADE are you using the "cell-based" or "OSS/irun" based flow (Simulation->Netlist and Run options)? Which version of the IC tools are you using (About->Help in the CIW) and which version of the simulator are you using? (ncsim -version will tell you).

    As mentioned in the forum guidelines, providing this information helps anyone responding here give you a more focussed answer.

    Regards,

    Andrew.

Reply

  • Sunil,

    How are  you running the simulation? Is it from the Hierarchy Editor AMS Plugin? Is it from the Analog Design Environment (with ams as the simulator)? If in ADE are you using the "cell-based" or "OSS/irun" based flow (Simulation->Netlist and Run options)? Which version of the IC tools are you using (About->Help in the CIW) and which version of the simulator are you using? (ncsim -version will tell you).

    As mentioned in the forum guidelines, providing this information helps anyone responding here give you a more focussed answer.

    Regards,

    Andrew.

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