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VHDL-AMS complie error

sr1857

 Dear All,

I am trying to create a testbench that includes a transducer written in VHDL-AMS and some standard components from analogLib. When I try to 'Netlist and run' a transient solution I get the following error. Could anybodypoint me in the right direction?

Many thanks,

Sunil.

file: /usr/local/cds-een/cadence/ius/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/ConnRules_18V_basic/connect/verilog.vams
ncvlog: *E,DLPAKW: Attempt to write connect connectLib.ConnRules_18V_full_fast:connect (VST) into a read-only library.
    connect connectLib.ConnRules_18V_full_fast:connect

 

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  • sr1857

    Hi Andrew,

    Many thanks for your reply. I use the Hierarchy Editor to initialize the AMS enviornment (Plugin>AMS then AMS>Initialize).Then I go to the Schematic Editor and open the ADE and run the simulation from there. I am using cell-based flow.The IC tools version is IC6.1.3.1.

     Any comments would be much appreciated.

    Regards,

    Sunil.

Reply
  • sr1857

    Hi Andrew,

    Many thanks for your reply. I use the Hierarchy Editor to initialize the AMS enviornment (Plugin>AMS then AMS>Initialize).Then I go to the Schematic Editor and open the ADE and run the simulation from there. I am using cell-based flow.The IC tools version is IC6.1.3.1.

     Any comments would be much appreciated.

    Regards,

    Sunil.

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