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VHDL-AMS complie error

sr1857

 Dear All,

I am trying to create a testbench that includes a transducer written in VHDL-AMS and some standard components from analogLib. When I try to 'Netlist and run' a transient solution I get the following error. Could anybodypoint me in the right direction?

Many thanks,

Sunil.

file: /usr/local/cds-een/cadence/ius/tools.lnx86/affirma_ams/etc/connect_lib/connectLib/ConnRules_18V_basic/connect/verilog.vams
ncvlog: *E,DLPAKW: Attempt to write connect connectLib.ConnRules_18V_full_fast:connect (VST) into a read-only library.
    connect connectLib.ConnRules_18V_full_fast:connect

 

Parents

  • Sunil,

    This generally means that your INCISIVE (or IUS) installation was not configured properly, but all you should need to do is add this to your cds.lib :

    ASSIGN AllLibs TmpRootDir path

    where path is the path to a writeable directory, typically under your working directory. This allows compilation of readonly stuff to go into that directory. 

    You could make it more specific by using:

    ASSIGN connectLib TMP path

    which means it will do it for just connectLib.

    You don't normally need to use the HED plugin and ADE - it would be one or the other.

    Andrew.

Reply

  • Sunil,

    This generally means that your INCISIVE (or IUS) installation was not configured properly, but all you should need to do is add this to your cds.lib :

    ASSIGN AllLibs TmpRootDir path

    where path is the path to a writeable directory, typically under your working directory. This allows compilation of readonly stuff to go into that directory. 

    You could make it more specific by using:

    ASSIGN connectLib TMP path

    which means it will do it for just connectLib.

    You don't normally need to use the HED plugin and ADE - it would be one or the other.

    Andrew.

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