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decoder implementation problem

kpkp
Hi all,
I want to implement analog 5 to 32 decoder in cadence virtuoso schematic editor. I have made 5 to 32 decoder using one 2-4 decoder and four 3-8 decoders. But at the time of simulation, I am getting an error saying that "some branches form rigid loops when connected to circuit"... I have attached all the schematics and error report herewith...Please help me if anybody can solve this...
Thanks in advance...
 
Parents

  •  OK, it's very simple. You have multiple sources for vdd in parallel. Since the voltage source is not part of the design, but part of the testbench, don't put it in the design schematics (you can't lay out the voltage source, after all). 

    Since your supply nets are global, you just need one vdd source at the top level from vdd! to ground, and then all will be OK.

    Whilst in theory you might think that it shouldn't matter having all these sources in parallel (since they are the same voltage), the more general problem is that this would lead to an unsolveable matrix (if they were slightly different voltages, say).

    Regards,

    Andrew.

Reply

  •  OK, it's very simple. You have multiple sources for vdd in parallel. Since the voltage source is not part of the design, but part of the testbench, don't put it in the design schematics (you can't lay out the voltage source, after all). 

    Since your supply nets are global, you just need one vdd source at the top level from vdd! to ground, and then all will be OK.

    Whilst in theory you might think that it shouldn't matter having all these sources in parallel (since they are the same voltage), the more general problem is that this would lead to an unsolveable matrix (if they were slightly different voltages, say).

    Regards,

    Andrew.

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