Stats

  • Locked Locked
  • Replies 5
  • Subscribers 126
  • Views 14948
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

How to integrate a full-custom designed layout with a semi-custom designed microprocessor.

Thommandram

Hello,

can someone tell me how to attach a memory/register file layout designed in(cadence virtuoso) with a Semi-Custom / Auto generated layout of a Microprocessor(the logic synthesis is to be done in rtl compiler and soc encounter is the pnr tool i use)?

I am using rtl compiler- physical, soc encounter. Just need help on what design flow to be followed. suggest/ give some ideas please.. 

Parents
  • Thommandram

    Hello,

    I have verilog codes - (of a microprocessor design.), tell me a way to do the logic and physical synthesis which satisfies the below conditions:

    I created register file/ RAM layout in cadence virtuoso. These register files are created with a novel architecture, and I want to add these in to the microprocessor design which is mentioned before.

    Please note that I am not creating memory or a RAM for the microprocessor in verilog codes. I am creating a custom-designed layout in cadence virtuoso to create the RAM.

    I want to know how to integrate the two design layouts together. Any suggestion/ ideas are welcome.

    1 easy method which comes to mind : DO the logic synthesis in Cadence RTL Compiler in regular fashion and then, while creating the layouts in SOC Encounter, leave a seperate space in the floorplan for the custom designed layout. So that, it can be attached later.

    Does this idea work? Kindly help me with an optimized design flow solution . please!!! 

Reply
  • Thommandram

    Hello,

    I have verilog codes - (of a microprocessor design.), tell me a way to do the logic and physical synthesis which satisfies the below conditions:

    I created register file/ RAM layout in cadence virtuoso. These register files are created with a novel architecture, and I want to add these in to the microprocessor design which is mentioned before.

    Please note that I am not creating memory or a RAM for the microprocessor in verilog codes. I am creating a custom-designed layout in cadence virtuoso to create the RAM.

    I want to know how to integrate the two design layouts together. Any suggestion/ ideas are welcome.

    1 easy method which comes to mind : DO the logic synthesis in Cadence RTL Compiler in regular fashion and then, while creating the layouts in SOC Encounter, leave a seperate space in the floorplan for the custom designed layout. So that, it can be attached later.

    Does this idea work? Kindly help me with an optimized design flow solution . please!!! 

Children
No Data

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.