How to integrate a full-custom designed layout with a semi-custom designed microprocessor.

Hello,

I have verilog codes - (of a microprocessor design.), tell me a way to do the logic and physical synthesis which satisfies the below conditions:

I created register file/ RAM layout in cadence virtuoso. These register files are created with a novel architecture, and I want to add these in to the microprocessor design which is mentioned before.

Please note that I am not creating memory or a RAM for the microprocessor in verilog codes. I am creating a custom-designed layout in cadence virtuoso to create the RAM.

I want to know how to integrate the two design layouts together. Any suggestion/ ideas are welcome.

1 easy method which comes to mind : DO the logic synthesis in Cadence RTL Compiler in regular fashion and then, while creating the layouts in SOC Encounter, leave a seperate space in the floorplan for the custom designed layout. So that, it can be attached later.

Does this idea work? Kindly help me with an optimized design flow solution . please!!! 

Hi Thommandram

The traditional way of mixed-signal layout integration is to export gds and physical verilog netlist from Encounter. The gds file is then re-imported into Virtuoso and added into the top level layout. The physical verilog netlist is used for top level LVS together with the schematic/netlist for the rest of the blocks.

With the introduction of openAccess, we no longer need to do gds translation. Please see COS solution 11736956 for more details on how to convert a LEF-based design to openAccess.

Best regards
Quek

Hello Thommandram,

In your first email you mentioned that you would like to use RTL Compiler - physical, it is going to produce a DEF file that you could use in EDI.

In order to easily be able to save form EDI into OA in order to avoid many translations (DEF) as well as loosing the connectivity (gds).

I assume you have a Virtuoso techfile. you need first to verify if you have a LEFDefaultRouteSpec constraint group, if you have one please make sure it is consistent in term of technology information with your LEF file. This is the first problem to solve. 

You can start EDI with the verilog and def you got from RTL compiler but using the OA reference libraries from Virtuoso, please make sure to make the library in which you are going to save your design as first in the list as we extract the technology information from this library or from the libraries attached to referenced to this one. The reference libraries will as well be very important during the save to Open Access

In term of design if you do the implementation into EDI you need at least to have a module description (module instantiation and port definition) of your block that you would like to add into Virtuoso, it would be great to have a preliminary layout from Virtuoso of this block in order to reserve the right area (prBoundary and pins) then you could consider it as a blackBox in term of timing or you can do some timing budgeting.

When you are back into Virtuoso you need to substitute the original floorplan of your Virtuoso block by the finale version. If you could layoutXL or LayoutCE it would check if you haven't introduced mismatch in term of connectivity when you have replace one cell by the other.

Best regards,
Alex

Dear Respectable Sir, Hope you will be fine. Dear Sir my query is that i design my custom nand gate library in cadence virtuoso including schematic and layout. Now i want to used this customized library in RTL compiler instead of standard cell during logic synthesis. what should i do because i am beginner and first time working on customized cell  .Your help will be appreciated. Thanks in advance 

Rather than asking a question in a nine-year old thread which is rather vague and open-ended and not that related to the original post (plus the forum guidelines explicitly ask you not to do this), I would suggest asking a new question, preferably in the Digital Implementation Forum since you're question is about RTL Compiler which is a Digital Implementation tool.