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How to integrate a full-custom designed layout with a semi-custom designed microprocessor.

Thommandram

Hello,

can someone tell me how to attach a memory/register file layout designed in(cadence virtuoso) with a Semi-Custom / Auto generated layout of a Microprocessor(the logic synthesis is to be done in rtl compiler and soc encounter is the pnr tool i use)?

I am using rtl compiler- physical, soc encounter. Just need help on what design flow to be followed. suggest/ give some ideas please.. 

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  • Quek

    Hi Thommandram

    The traditional way of mixed-signal layout integration is to export gds and physical verilog netlist from Encounter. The gds file is then re-imported into Virtuoso and added into the top level layout. The physical verilog netlist is used for top level LVS together with the schematic/netlist for the rest of the blocks.

    With the introduction of openAccess, we no longer need to do gds translation. Please see COS solution 11736956 for more details on how to convert a LEF-based design to openAccess.

    Best regards
    Quek

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  • Quek

    Hi Thommandram

    The traditional way of mixed-signal layout integration is to export gds and physical verilog netlist from Encounter. The gds file is then re-imported into Virtuoso and added into the top level layout. The physical verilog netlist is used for top level LVS together with the schematic/netlist for the rest of the blocks.

    With the introduction of openAccess, we no longer need to do gds translation. Please see COS solution 11736956 for more details on how to convert a LEF-based design to openAccess.

    Best regards
    Quek

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