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Does Cadence 6.1.5 support SpectreVerilog simulator?

ericliu

 I recently switched from Cadence 5 to Cadence6.1.5. Someone told me that mixed-signal simulation using SpectreVerilog is not supported in Cadence 6. Is that true? So what are the supported simulators in Cadence 6.1.5. What is the best (fastest) simulator to simulate a design which contains both schematic and verilog blocks. Many thanks.

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  • Hi Quek, Can I use spectre Verilog in IC615? Is there any tutorial available.? I want to test a simple 8bit adder (RTL) using ideal_adc and ideal_dac to verify its working in virtuoso. I am having following error at simulation phase. ************************************************ Transient Analysis `tran': time = (0 s -> 10 ms) ************************************************ Error found by spectre during initialization. ERROR (SPECTRE-16325): Error while starting the attached simulator. The verilog code I am using is pretty much simple (I am doing some basic mistake at simulation level) Awais
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  • Hi Quek, Can I use spectre Verilog in IC615? Is there any tutorial available.? I want to test a simple 8bit adder (RTL) using ideal_adc and ideal_dac to verify its working in virtuoso. I am having following error at simulation phase. ************************************************ Transient Analysis `tran': time = (0 s -> 10 ms) ************************************************ Error found by spectre during initialization. ERROR (SPECTRE-16325): Error while starting the attached simulator. The verilog code I am using is pretty much simple (I am doing some basic mistake at simulation level) Awais
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