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Mark net feature in layout

mailavj

Hello

 I am an Analog IC design student. In my university we are using cadence IC614. At the moment I am using it to design an amplifier (Schematics and Layout). We are using libraries from AMS foundry for this purpose. I have laid down an NMOS transistor and attached wires to its source, drain and gate. When i do Connectivity -- Nets -- Mark in layout editor and select drain net, it shows short with source net. However there is only on transistor in the layout editor at the moment and its not connected with anything else. I am not sure why this is happening. Please advise.

 Thank you

Aravind 

Parents

  • Hi Aravind

    I think you can resolve the problem as follows:
    a. Invoke marknet cmd
    b. Press F3 to display marknet options form
    c. Choose "Select via"
    d. Unselect the via connecting your metal1 and diffusion

    In your case, marknet is using all the vias and hence connects everything through the substrate.

    Best regards
    Quek

Reply

  • Hi Aravind

    I think you can resolve the problem as follows:
    a. Invoke marknet cmd
    b. Press F3 to display marknet options form
    c. Choose "Select via"
    d. Unselect the via connecting your metal1 and diffusion

    In your case, marknet is using all the vias and hence connects everything through the substrate.

    Best regards
    Quek

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