Beginner questions: Verilog-a - Custom Models

Hi everybody, I am creating a custom transtistor model with verilog-a and using it at a symbol with ADE and I have some questions:

1)Is there a dedicated way to parse verilog code? so far the thing I have been doing is editing the code inside its cell and then when I close it after a while verilog parser fires up and gives me the errors / warnings. It there a way to do this in a better way, sinse I cannot see the warnings but just the errors? 

2) The above I believe causes me some errors since for a weird reason sometimes updating verilog code does not affect the symbol I created, and each time I update the code I have to create a new symbol. Is there a way to update the symbol?

3)Is there an official verilog-a manual for the features cadence supports?

cheers,

Sotiris