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Is there a way to make Cadence point to the error?

tony4tony

Hi All,

                I am completely new to Cadence and am just doing my second tutorial. So please forgive my ignorance. I am basically trying to make a inverter layout. I am getting error regarding

"Violated Rules. 

1 M1R1 Minimum density  of MET1 area [%] = 30

1 M2R1 Minimum density  of MET2 area [%] = 30

1 M3R1 Minimum density  of MET3 area [%] = 30 "

                     I was told I could get rid of the error by  setting "no coverage" when I run DRC. But I would like to know what the error is and how to fix it. I tried googling and searcched some forums. But couldnt find any answer. Can somebody please help?

Many Thanks,

Tony 

 

Parents
  • Quek

    Hi Tony

    This is the correct forum. Every layout must meet certain density requirement so that it can be properly fabricated by the foundry. E.g. if the total area of your cellview is 10um2 ("um2" means micro-metre square) and you only a single piece of M1 metal with area 1um2, then it means that your M1 density is 100% * 1/10 = 10% and hence your cell fails the requirement of 30%.

    Modern foundries use CMP (chemical mechanical polishing) processes to smoothen the surface of the wafers and if the density of each layer is not uniform, the polishing of the wafer would result in uneven wire thickness and hence changes the intended characteristics of the process.

    You can read more about this from any IC design layout textbooks. E.g.
    http://www.amazon.com/IC-Layout-Basics-Practical-Guide/dp/0071386254


    Best regards
    Quek

Reply
  • Quek

    Hi Tony

    This is the correct forum. Every layout must meet certain density requirement so that it can be properly fabricated by the foundry. E.g. if the total area of your cellview is 10um2 ("um2" means micro-metre square) and you only a single piece of M1 metal with area 1um2, then it means that your M1 density is 100% * 1/10 = 10% and hence your cell fails the requirement of 30%.

    Modern foundries use CMP (chemical mechanical polishing) processes to smoothen the surface of the wafers and if the density of each layer is not uniform, the polishing of the wafer would result in uneven wire thickness and hence changes the intended characteristics of the process.

    You can read more about this from any IC design layout textbooks. E.g.
    http://www.amazon.com/IC-Layout-Basics-Practical-Guide/dp/0071386254


    Best regards
    Quek

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