Is there a way to make Cadence point to the error?

 Hi Tony,

You also need to consider which cell in terms of how close you are to the top level chip/IP in terms of hierarchy.  It makes no sense to check density on a small cell.  Typically density is checked on higher level cells or very large cells in terms of area.  This is because density is considered over the entire die.  A tiny cell may meet density but when placed into the chip the areas around it might be sparse and so you'll have a density issue.

Are you working on IP or the whole chip?  Which process are you using?

Generally the older, larger geometry processes like .13 and above will have more forgiving density rules.  Smaller processes like 65nm, 40nm, and below have much more stringent requirements and include multi level metal proximity rules.

 If you're doing IP for an SOC then you'll need to take care with the edges of your IP where the abutting neighboring layouts are unknown.

Also be aware that the bounding box of cells also includes/surrounds the entirety of the labels/txt displays and can give you false errors if texts "hang out" outside the edges of actual active layers at the edge of your cell.

A good way to proceed is just visually check each metal layer over your entire layout and any large open areas, especially close to denser areas will have problems.

 Finally all the large fabs provide density filling routines within Assura and/or Calibre so that you do not have to do this by hand.  There's usually an elaborate suite of special "fill" metal layers, fill vias, and corollary blocking layers. Some fabs/processes (like Jazz) do the fill for you unless you request otherwise.  Before spending a lot of time carefully making your layout meet density it might be good to check to see what your fab requirements are, what/where on the filling routines, and how to use.

Does this help?

 Hi Tony,

You also need to consider which cell in terms of how close you are to the top level chip/IP in terms of hierarchy.  It makes no sense to check density on a small cell.  Typically density is checked on higher level cells or very large cells in terms of area.  This is because density is considered over the entire die.  A tiny cell may meet density but when placed into the chip the areas around it might be sparse and so you'll have a density issue.

Are you working on IP or the whole chip?  Which process are you using?

Generally the older, larger geometry processes like .13 and above will have more forgiving density rules.  Smaller processes like 65nm, 40nm, and below have much more stringent requirements and include multi level metal proximity rules.

 If you're doing IP for an SOC then you'll need to take care with the edges of your IP where the abutting neighboring layouts are unknown.

Also be aware that the bounding box of cells also includes/surrounds the entirety of the labels/txt displays and can give you false errors if texts "hang out" outside the edges of actual active layers at the edge of your cell.

A good way to proceed is just visually check each metal layer over your entire layout and any large open areas, especially close to denser areas will have problems.

 Finally all the large fabs provide density filling routines within Assura and/or Calibre so that you do not have to do this by hand.  There's usually an elaborate suite of special "fill" metal layers, fill vias, and corollary blocking layers. Some fabs/processes (like Jazz) do the fill for you unless you request otherwise.  Before spending a lot of time carefully making your layout meet density it might be good to check to see what your fab requirements are, what/where on the filling routines, and how to use.

Does this help?