Howto read port currents when having multi-terminal bus ports in VerilogA ?

Hello,

I am using multi-terminal ports in VerilogA, and would like to extract the current on one of the bus-lines using the construct I(<myport[thisline]>) where thisline is a genvar. As far as I understand the VerilogA reference manual and the Verilog-AMS specifications this should be possible, however the syntax checker (when saving the veriloga view in the library) does not allow this construct.

Am I doing something wrong ? 

**  Below the declaration of my modules and the ports :

 module qnrmesh2d(majport,minport);
   
   // Majority carriers terminals  
   inout [1:`QNRMESH2D_NPORTS] majport;
   electrical [1:`QNRMESH2D_NPORTS] majport;

   // Minority carriers terminals  
   inout [1:`QNRMESH2D_NPORTS] minport;
   electrical [1:`QNRMESH2D_NPORTS] minport;

** Example statement I would like to construct :

for (thisPort = 1; thisPort < `QNRMESH2D_NPORTS; thisPort = thisPort + 1) begin
    ...
    Enorm[thisPort] = I(<majport[thisPort]>)/(Area[thisPort]*Sigma_maj);

 ** But the syntax checker only allowed me to make the following (which I don't like because I did not want to create branches to ground) : 

for (thisPort = 1; thisPort < `QNRMESH2D_NPORTS; thisPort = thisPort + 1) begin
    ...
    Enorm[thisPort] = I(majport[thisPort])/(Area[thisPort]*Sigma_maj);