Parameterized VHDL using generics and ADE-AMS simulation

Hello all,

I would like to use VHDL generics to parameterize the behavior of signals generated by a VHDL model (see attachment). The VHDL model I then want to simulate using the AMS simulator in ADE (preferably using adexl global variables). 

To generate the views in the library manager I use File->Import->VHDL. Virtuoso then creates three views: behavioral, entity and symbol. The symbol instantiated in a schematic is then offering a CDF Parameter to set the value of the generic. If I keep it at the default parameter (keep the parameter field empty) the mixed mode simulation correctly simulates. If I then set the parameter to the _same_ value as the default value the simulation does not finish giving following error:

ncsim: *W,TRNEGT: negative time in wait statement or transaction.

I also tried to set the generics using  Edit->Properties->VHDL... from the schematic editor. But no change in behavior.
I also discovered the 'additional arguments (elaborator)' option from the AMS simulator but if I add -generic offset_time=>50 I get following warning in the elaborator log:

...
    -generic offset_time=

ncelab: *W,EVBGSN: bad generic association syntax (offset_time=).

It seems to me that the cdl parameter is not correctly parsed / passed to the elaborator. Any ideas or suggestions to solve this issue are very welcome.

Best wishes, Lukas 

Versions I am using:

virtuoso: IC6.1.5-64b.500.6
spectre: 10.1.1.200.isr13

@(#)$CDS: amsdesigner version 6.1.5-64b 09/07/2011 00:42 $
Cadence® Hierarchy Editor, version 32.10.s008
@(#)$CDS: cdsHierEditor version 32.10 08/17/2011 22:55 (cat91amd) $
@(#)$CDS: amsdirect version 6.1.5-64b 09/07/2011 00:57 (sjfdl050) $
ncvlog(64)      10.20-s073