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Shift register random initialization - how to proceed ?

Pavel47

Hello,

For my testbench I need some custom shift register, that randomly initialized. Here below is its code.

Compilation passes, but elaboration doesn't.

Any solution ?

Thanks in advance.

Pavel.

 module Pixel_v0 (input Din, CLK, output Dout );
   parameter SEED = 33;
   reg [15:0] DATA;
   assign Dout = DATA[15];

   initial DATA = random(SEED);

   generate
      genvar  i;
      for (i = 0; i < 15; i=i+1) begin: DFF
     if (i==0)
       always @(posedge CLK)
         DATA[i] <= Din;
     always @(posedge CLK)
       DATA[i+1] <= DATA[i];
      end
   endgenerate

endmodule

  • Andrew Beckett

    Not really the best forum for a Verilog question, but I should be able to answer it. First it's $random, and secondly the seed has to be an integer, a reg,  or a time variable (according to the 1364-2001 LRM). So this compiles and elaborates:

       integer INTSEED=SEED;
       assign Dout = DATA[15];

       initial DATA = $random(INTSEED);

    If this doesn't answer your question, I'll shift it to the right forum.

    Andrew

  • Pavel47

     Perfect ! Thanks Andrew.

    One more question (if possible), more related to the tool - I tried to add the possibility to edit parameter value from schematic. For this I procedded as follows:

    • CIW->Tools->CDF->Edit
    • Set library and cell
    • My parameter were already in the table (with all neccessary settings, that I've picked from some other post)
    • Click Ok
    • Returned to Schematic
    • Click refresh

    Nothing changed - my paramerers didn't appear close to symbols.

    Regards

    Pavel.

  • Pavel47

     In order to displa/edit the parameter value of a particular Verilog-type instance, one should proceed as follows:

    1. Type "Q"

    2.  Click on instance

    3. In the opened window change CDF parameter of view to verilog

    4. Change Display property to both

    5. Specify the desired parameter value in the corresponding textedit box

    But how to proceed if I want that the particular parameter were displayed by default when I instantinate this module. Probably I should change something in the symbol view of the component ?

    Thanks.

    Pavel.

  • Andrew Beckett

    Pavel,

    Your symbol needs to have cdsParam(N) labels - these must be of type ILLabel - the easiest way to achieve that is to use Create->Label in the symbol editor, then set Label Choice to "analog device annotate" - you'll need to change the cdsParam(1) to cdsParam(2) etc - the idea is that each number represents a slot for a parameter to be displayed.

    Then go to Tools->CDF->Edit CDF, set the type to "Base" rather than "Effective" and navigate to your cell. Go to the Interpreted Labels tab (or section if using IC5141), and in the Parameters tab you can set cdsParam to display Instance/CDF Parameters, and then define the parameter names you want it to display. Take a look at (say) nmos4 from analogLib to get an idea as to how this is set up to show model, w, l etc.

    Regards,

    Andrew.

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