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Shift register random initialization - how to proceed ?

Pavel47

Hello,

For my testbench I need some custom shift register, that randomly initialized. Here below is its code.

Compilation passes, but elaboration doesn't.

Any solution ?

Thanks in advance.

Pavel.

 module Pixel_v0 (input Din, CLK, output Dout );
   parameter SEED = 33;
   reg [15:0] DATA;
   assign Dout = DATA[15];

   initial DATA = random(SEED);

   generate
      genvar  i;
      for (i = 0; i < 15; i=i+1) begin: DFF
     if (i==0)
       always @(posedge CLK)
         DATA[i] <= Din;
     always @(posedge CLK)
       DATA[i+1] <= DATA[i];
      end
   endgenerate

endmodule

Parents
  • Andrew Beckett

    Not really the best forum for a Verilog question, but I should be able to answer it. First it's $random, and secondly the seed has to be an integer, a reg,  or a time variable (according to the 1364-2001 LRM). So this compiles and elaborates:

       integer INTSEED=SEED;
       assign Dout = DATA[15];

       initial DATA = $random(INTSEED);

    If this doesn't answer your question, I'll shift it to the right forum.

    Andrew

Reply
  • Andrew Beckett

    Not really the best forum for a Verilog question, but I should be able to answer it. First it's $random, and secondly the seed has to be an integer, a reg,  or a time variable (according to the 1364-2001 LRM). So this compiles and elaborates:

       integer INTSEED=SEED;
       assign Dout = DATA[15];

       initial DATA = $random(INTSEED);

    If this doesn't answer your question, I'll shift it to the right forum.

    Andrew

Children
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