gen form source issue

The message is pretty clear - it's telling you that there's no terminal (i.e. no pin) called biasn_lvgen in the opamp_a1p8 layout. Presumably you have an instance of this opamp in your design, and when the gen from source is done, it needs to assign the appropriate connectivity on each terminal of the resulting instance in the layout. The instance in the schematic will have connections to each terminal on the placed symbol; when the corresponding opamp layout is placed in your generated layout, it needs to know how to connect up each of those pins - if there's no pin on the opamp layout, it can't connect to it.

 So something is wrong with the layout of your opamp_a1p8; it's missing a pin.

Andrew.

 Hey Andrew,
Sorry for replying onold topic.

I have the similar issue , I have instance in my schematic view and it has all pins( I checked via SKILL command cvId~>instances~>instTerms~>name) , but when I try to convert it to layout using Create->Geerate->all from sorurce then It's giving me error that  p, li { white-space: pre-wrap; }

Cannot create instance terminal on layout instance '|I22' because the instance master '[lib]/[cell]/layout' does not have a corresponding terminal 'b'.

when I open the master layout it says" You can't edit the layout , Opening the layout in Read only mode, No data on lock availablle ". So is it possible this error can be because of this non-editable mode ?

My guess is because the instance is a transistor, and the pcell for the transistor hasn't implemented a pin for the bulk?

Andrew.