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Glitch(Spike) in the output..

Raki87
Hello..I am new to cadence, I was trying to simulate the simple 'd' latch using cadence, but i noticed that there is a spike in the output going above my supply voltage and below the ground level( i have rise and fall time of clock and D input as 5 ns). When i increase the rise time and fall time of my clock(D) the glitch is reduced, but my fellow students who use the same version of the cadence, are getting the correct output even for rise , fall time of 5n sec. i get this glitch only when i simulate the schematic and not in layout simulation.. Is there anythin i missed in my transient analysis? because of this glitch my desired attributes are not met, please suggest me a way out..Thanks!
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  •  Hi Raki87,

     can you please clarify what tools are you using? As far as RTL synthesis is concerned, most if not all synthesis tools in the market place do not perform any glitch mitigation so it is left to user to design circuity that is glitch tolerant. In fact, this is one of the reasons, why most synthesis tools are meant to be used for synchronous design and not asynchronous design. Glitches in such cases would lead to hazards, etc.

     gh-

Reply

  •  Hi Raki87,

     can you please clarify what tools are you using? As far as RTL synthesis is concerned, most if not all synthesis tools in the market place do not perform any glitch mitigation so it is left to user to design circuity that is glitch tolerant. In fact, this is one of the reasons, why most synthesis tools are meant to be used for synchronous design and not asynchronous design. Glitches in such cases would lead to hazards, etc.

     gh-

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