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Convert schematic to Verilog file

Myskill

 Hi All,

            could you please help how to get verilog file from schematic.

 

Regards,

Rambabu

Parents
  • Myskill

     I am following following procedure for creation oa2verilog  

    Open a shell from the library manager using File->Open shell window. This shell will be initialized with the necessary environment variables for the next step.

    In the new shell use:

    oa2verilog -lib <name of library> -cell <name of cell> -view schematic -verilog <name of cell>.v -recursive

    Substitute the lib name and cell name for the specific cell to netlist.

    This is limited to a cell without hierarchy

     I want generate it for hierachy Could you please help on this.

    Regards,

    Rambabu

Reply
  • Myskill

     I am following following procedure for creation oa2verilog  

    Open a shell from the library manager using File->Open shell window. This shell will be initialized with the necessary environment variables for the next step.

    In the new shell use:

    oa2verilog -lib <name of library> -cell <name of cell> -view schematic -verilog <name of cell>.v -recursive

    Substitute the lib name and cell name for the specific cell to netlist.

    This is limited to a cell without hierarchy

     I want generate it for hierachy Could you please help on this.

    Regards,

    Rambabu

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