could you please help how to get verilog file from schematic.
I am following following procedure for creation oa2verilog
Open a shell from the library manager
using File->Open shell window. This shell will be initialized with the
necessary environment variables for the next step.
In the new shell use:
oa2verilog -lib <name of library>
-cell <name of cell> -view schematic -verilog <name of cell>.v
Substitute the lib name and cell name
for the specific cell to netlist.
This is limited to a cell without hierarchy
I want generate it for hierachy Could you please help on this.