could you please help how to get verilog file from schematic.
Either Tools->NC Verilog (from the CIW), or Launch->Simulation->NC Verilog (from a schematic).
Any shell command for generating verilog code from schematic hierarchically from top cell to bottom
Set it up in the UI as described above, and then you can do:
si -command netlist -batch pathToRunDirectory
I am following following procedure for creation oa2verilog
Open a shell from the library manager
using File->Open shell window. This shell will be initialized with the
necessary environment variables for the next step.
In the new shell use:
oa2verilog -lib <name of library>
-cell <name of cell> -view schematic -verilog <name of cell>.v
Substitute the lib name and cell name
for the specific cell to netlist.
This is limited to a cell without hierarchy
I want generate it for hierachy Could you please help on this.
I already explained how to do this with the Verilog netlister. oa2verilog is much lower level and does not support all of the complex control that the OSS Verilog netlister does. I would not recommend you trying to use oa2verilog (it doesn't have the concept of switch and stop list, for example, nor does it support config views).