I have a question regarding naming conventions in layout and schemtics. Suppose I use vdd! and vss! to represent in my layout for vdd and gnd. When i run a testbench simulation, i assign the local value vdd! to the master value vdd. But i still see that my ouput is not as expected. Could anyone help me with this?Thanks
Not enough detail I'm afraid. You didn't say what simulator you're using, which version of the tools you are using, or what you mean by "I assign the local value vdd! to the master value vdd". Or what the output is that you're expecting or what it is actually giving, or what your circuit is. Unfortunately we're not clairvoyant, so could you provide some more details to describe precisely what you're doing, and precisely what does not work?