I have a question regarding naming conventions in layout and schemtics. Suppose I use vdd! and vss! to represent in my layout for vdd and gnd. When i run a testbench simulation, i assign the local value vdd! to the master value vdd. But i still see that my ouput is not as expected. Could anyone help me with this?Thanks
Not enough detail I'm afraid. You didn't say what simulator you're using, which version of the tools you are using, or what you mean by "I assign the local value vdd! to the master value vdd". Or what the output is that you're expecting or what it is actually giving, or what your circuit is. Unfortunately we're not clairvoyant, so could you provide some more details to describe precisely what you're doing, and precisely what does not work?
Sorry for the lesser details. I am using spectre.I have a problem to use global power and ground in Cadence6.
I use vdd! and vss! in my schematics. They are recognized in different hierarchy in schematic simulation, so no problem. However, they are a problem when I would like to run a testbench simulation. Either I use vdd and gnd symbols and directly connects to a block of the circuit or another way is giving pins and name them vdd! and gnd!. In either way, there will be no physical nodes to connect to a power source and ground. There is no problem with spectere simulaion, but when I try to run a testbench simulation the problem arises.
I know there is some method where in the testbench simulation ,I edit the properties of the symbol and use netset and assign them to vdd and gnd. But when i tried this with the inverter the expected inverter output is not seen.
Could you please tell me the steps as in how assign the local values to the global ones?