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  3. QRC extraction & BUS

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QRC extraction & BUS

Zdeno
Zdeno over 12 years ago

Hi guys,

I have problem with simulation of BUSes in extraction view. I use IC615, Assura QRC. First I simulate gate-level verilog netlist with AMS. In verilog I have bus cnf_reg_analog<15:3> and I can plot results from this bus. Then I create abstract with Encounter, then layout. Run Assura LVS -> Clean. Run Assura QRC -> create extracted view.

The problem is that in layout the bus net name looks like cnf_reg_analog<15> and in the extracted view looks like cnf_reg_analog(15). Note the brackets. And ADEXL (AMS simulator) complains:

 

ERROR (WIA-1006): Unable to plot expression <VT("/cnf_reg_analog<15>" "/home/cadence/simulation/TEST_BENCHES_PHpix1/PHpix1_channel_digi_tb/adexl/results/data/Interactive.12/psf/tran")>

because it does not evaluate to an object that can be plotted, like a waveform or

parametric wave. See the Visualization & Analysis Tool documentation for information

about the types of objects that can be plotted in Visualization & Analysis Tool. Only

the expressions that evaluate to those objects can be plotted.

*Warning* Wave2 is not a waveform object that can be displayed and

will be DELETED automatically.

name: "/cnf_reg_analog<15>"

So I assume that the problem is in bus extraction and brackets, but I do not know how to correct it.

I attached the properties of the net in layout and in extracted view for better understanding.

Do you have any idea how to simulate the BUS in extracted view?

Thank you, Zdeno

 layout

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  • Quek
    Quek over 12 years ago

    Hi Zdeno

    You can convert the round brackets to angled brackets during extracted view generation using the skillscript in solution 11290520.


    Best regards
    Quek

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  • Quek
    Quek over 12 years ago

    Hi Zdeno

    You can convert the round brackets to angled brackets during extracted view generation using the skillscript in solution 11290520.


    Best regards
    Quek

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