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Pnoise analysis

Jithin

Hi,

I have been designing a PLL which gives an output frequency in the range (400-500)MHz to the reference input frequency of (20-25)MHz.So for doing the pnoise analysis I have added the PSS as well as  Pnoise analysis

I have  made the following as setup for the analysis for a frequency of 500MHz. I have chosen 1) shooting method instead of harmonic balance 2)beat frequency to be the output of the divider (divider ratio is 20) that is 25MHz and also output of the PLL is selected as divider out in Pnoise tab. But it seems that the PSS is not converging and thus pnoise is failing.

So please direct me with the procedure for PSS as well as Pnoise for a PLL not for VCO alone.   

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  • Frank Wiedmann

    Hi Ben,

    I suggest that you take a look at the PLL Verification Workshop, which is available for download at http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/Custom_IC_Design/ApplicationPackages/CIC_RAK_Home.htm (an ADC Verification Workshop can also be downloaded there).

    Best regards,

    Frank

Reply
  • Frank Wiedmann

    Hi Ben,

    I suggest that you take a look at the PLL Verification Workshop, which is available for download at http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/Custom_IC_Design/ApplicationPackages/CIC_RAK_Home.htm (an ADC Verification Workshop can also be downloaded there).

    Best regards,

    Frank

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