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Pnoise analysis

Jithin

Hi,

I have been designing a PLL which gives an output frequency in the range (400-500)MHz to the reference input frequency of (20-25)MHz.So for doing the pnoise analysis I have added the PSS as well as  Pnoise analysis

I have  made the following as setup for the analysis for a frequency of 500MHz. I have chosen 1) shooting method instead of harmonic balance 2)beat frequency to be the output of the divider (divider ratio is 20) that is 25MHz and also output of the PLL is selected as divider out in Pnoise tab. But it seems that the PSS is not converging and thus pnoise is failing.

So please direct me with the procedure for PSS as well as Pnoise for a PLL not for VCO alone.   

  •  Hi Jithin,

    Cadence has a methodology for simulating the pnoise of a PLL in lieu of a VCO. Have you examined either of these?

    http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=dt;q=cic_design_entry_sim/PLL.pdf

    http://support.cadence.com/wps/PA_DocumentViewer/pubs//spectreRF/spectreRF11.1/spectreRF.pdf

    (Chapter 9 "Noise-Aware PLL Flow")

    Shawn

  • Thank you smlogan,

    I have already gone through the above mentioned pdf and the situation is such that I'm not using a macro model and what I have been doing is that I have designed a PLL and trying to analyse its noise performance and  so my set up looks  as below .
    I used a port as my input reference  through which I generate a pulse of frequency 25MHz and the output is assumed to be 500 MHz .
    In PSS tab I have chosen Engine as Shooting and the beat frequency to be the output of the divider and also in the Pnoise tab I have chosen output to be a voltage and chosen the divider output and also I consider noise type as Jitter.
    So please again go through this and kindly give some ideas why my PSS is not converging and so failing the noise analysis.

    Thank you.
  • Hi Jothin,

    There was no file attached to view your analysis. However, I would suggest you consider breaking the analysis into several analyses - one for the VCO, phase detector, and divider if you do not want to resort to a macro model. Please consider the complexity of the simulation you are trying to perform. You are asking to find the steady-state transient solution of a system with local and global feedback whose components react in a high non-linear fashion. It is not surprising (to me anyway) that you are experiencing convergence issues with PSS.

    By examining the noise contributions of each component, not only will you greatly simply the analyses, but you will also gain insight into the relative noise contributions of each component and how they impact your final requirement. This will allow you to optimize those components that most impact your end requirement.

    Shawn

  • Hi Shawn, Jithin,

    The PLL Noise Aware flow is no longer recommended. It is being (or has been) removed from the documentation in MMSIM12.1.

     You may also want to look at transient/transient noise analysis.

     

    Best regards,

    Tawna

  • Thank you Tawna and Shawn for your kind reply.

  • Hello,

    What is recommended PLL analysis flow in Cadence in IC6.16 with MMSIM13.1 at this moment in time?

    Is it phase and voltage domain analysis as presented in "Virtuoso Spectre Circuit Simulator RF Analysis Library Reference" (Version 13.1)?

    Could you explain why the noise-aware PLL flow has been discontinued?

    Kind Regards,

    Ben

  •  Hi Ben,

    The PLL Noise Aware flow was discontinued for a number of reasons.  I won't go into all of them here.  One being the database associated contained proprietary data/IP from the Cadence RF Methodology Kit.  As such, certain legal documents (SPLA+ SPLA Kit exhibit) to be signed before the database could be released. It was not available to University students as well.    There were limitations with some of the models in the PLL Noise Aware flow database. 

    Best regards,

    Tawna

     

  • In addition to the reasons Tawna gave, it proved difficult to support the many different architectures of subblocks used in PLLs, and we found that there wasn't significant adoption of the technology to warrant greater investment in improving the technology, especially as in many cases people could either use behavioural simulation of the entire PLL or use of phase-domain modelling approaches.

    In fact we have some upcoming events in Europe which cover PLL verification (as well as ADC verification) and which will talk about using a phase-domain modelling approach (follow the link to see the details)

    Regards,

    Andrew

  • Hi Ben,

    I suggest that you take a look at the PLL Verification Workshop, which is available for download at http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:DocumentViewer;src=wp;q=ProductInformation/Custom_IC_Design/ApplicationPackages/CIC_RAK_Home.htm (an ADC Verification Workshop can also be downloaded there).

    Best regards,

    Frank

  • Thanks Frank- I meant to mention those. These are aligned with the presentation material that we're using in the upcoming Technology on Tour events in Europe, and earlier similar seminars in North America.

    Regards,

    Andrew.

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