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Global signals and spiceIn

kvntien

Hi all,

I am trying to import a CDL netlist using Spice In to generate a schematic view. However, I would like to keep the VDD and VSS pins local. When the import process calls conn2sch, conn2sch insists on appending a '!' to those net names because it thinks they should be global...

In my CDL netlist, there is no *.GLOBAL or *.PIN control statement, and the subcircuit header reads as

.SUBCKT cell1 Y VDD VSS A

I generated just a netlist view and sure enough the VDD and VSS signals in the view have isGlobal set to 't'. Where does this occur in the translation process, and how can I prevent that from happening?

 Thanks!

-Kevin 

Parents

  • I don't see this. I just imported this CDL netlist:

    * example of block with supplies
    .SUBCKT blockWithSupplies Y A VDD VSS
    MP1 Y A VDD VDD pch w=2u l=0.5u
    MN1 Y A VSS VSS nch w=1u l=0.5u
    .ENDS

    using this devMap:

     -- Device Mapping file generated from SpiceIn GUI
    devSelect := pfet pmos4
            propMatch := pch

    devSelect := nfet nmos4
            propMatch := nch

    (I had analogLib as a reference library, and had chosen CDL as the input language).

    I ran this with both the normal schematic generation and also the Analog schematic generation. The ASG picture is below. Checking in the database, VDD and VSS signals don't have isGlobal set.

    I'm using IC6.1.5.500.16.2 (so ISR16).

    Regards,

    Andrew.

     

Reply

  • I don't see this. I just imported this CDL netlist:

    * example of block with supplies
    .SUBCKT blockWithSupplies Y A VDD VSS
    MP1 Y A VDD VDD pch w=2u l=0.5u
    MN1 Y A VSS VSS nch w=1u l=0.5u
    .ENDS

    using this devMap:

     -- Device Mapping file generated from SpiceIn GUI
    devSelect := pfet pmos4
            propMatch := pch

    devSelect := nfet nmos4
            propMatch := nch

    (I had analogLib as a reference library, and had chosen CDL as the input language).

    I ran this with both the normal schematic generation and also the Analog schematic generation. The ASG picture is below. Checking in the database, VDD and VSS signals don't have isGlobal set.

    I'm using IC6.1.5.500.16.2 (so ISR16).

    Regards,

    Andrew.

     

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