I am trying to import a CDL netlist using Spice In to generate a schematic view. However, I would like to keep the VDD and VSS pins local. When the import process calls conn2sch, conn2sch insists on appending a '!' to those net names because it thinks they should be global...
In my CDL netlist, there is no *.GLOBAL or *.PIN control statement, and the subcircuit header reads as
.SUBCKT cell1 Y VDD VSS A
I generated just a netlist view and sure enough the VDD and VSS signals in the view have isGlobal set to 't'. Where does this occur in the translation process, and how can I prevent that from happening?
Right... I understand that post and had already read it, but I am having a different issue (and also not using CDL In, but Spice In).
I /want/ my pin names to be just VDD and VSS, but the translation process forces them to VDD! and VSS! independent of the presence or lack thereof of a *.GLOBAL statement.
In the Dracula documentation for how it handles CDL netlists, 'VDD' and 'VSS' are in the list of names that the power/ground pins must have. Does anyone know if this is true for the Assura parser that Spice In uses? In which case, does the parser auto-mark such signal names as global regardless of what else is in the CDL netlist?
I don't see this. I just imported this CDL netlist:
* example of block with supplies.SUBCKT blockWithSupplies Y A VDD VSSMP1 Y A VDD VDD pch w=2u l=0.5uMN1 Y A VSS VSS nch w=1u l=0.5u.ENDS
using this devMap:
-- Device Mapping file generated from SpiceIn GUIdevSelect := pfet pmos4 propMatch := pchdevSelect := nfet nmos4 propMatch := nch
(I had analogLib as a reference library, and had chosen CDL as the input language).
I ran this with both the normal schematic generation and also the Analog schematic generation. The ASG picture is below. Checking in the database, VDD and VSS signals don't have isGlobal set.
I'm using IC18.104.22.1680.16.2 (so ISR16).
First, thanks so much for trying to reproduce the issues, Andrew, I appreciate it a lot.
Unfortunately, I tried with your minimal example, and I still see the same issues... my generated schematic (analogue) is the same in every regard except for the VDD and VSS pins; conn2sch still warns that VDD and VSS are supposed to be global and appends a '!'. I'm importing into a library with no techfile attached, and with no PDK customisations, too...
We're running ISR12, so maybe that's the issue?
Either way, any ideas where this might be tripping up? Odd default settings in the Assura parser hidden away somewhere?