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Global signals and spiceIn

kvntien

Hi all,

I am trying to import a CDL netlist using Spice In to generate a schematic view. However, I would like to keep the VDD and VSS pins local. When the import process calls conn2sch, conn2sch insists on appending a '!' to those net names because it thinks they should be global...

In my CDL netlist, there is no *.GLOBAL or *.PIN control statement, and the subcircuit header reads as

.SUBCKT cell1 Y VDD VSS A

I generated just a netlist view and sure enough the VDD and VSS signals in the view have isGlobal set to 't'. Where does this occur in the translation process, and how can I prevent that from happening?

 Thanks!

-Kevin 

Parents

  • Hi Kevin,

    I just tried it in ISR12, and got:

    WARNING (CONN2SCH-136): The cell view terminal VDD is connected to a global signal VDD. The cell view
    terminal name will be suffixed with !.
    WARNING (CONN2SCH-136): The cell view terminal VSS is connected to a global signal VSS. The cell view
    terminal name will be suffixed with !.
    WARNING (CONN2SCH-134): The signal VDD is a global signal but does not end with '!'.
    WARNING (CONN2SCH-134): The signal VSS is a global signal but does not end with '!'.

    And I see the pins as being VDD! etc. I don't get this in IC615 ISR16. A bit of searching, I found CCR 910263 which implemented this (unfortunately I can't quite see which subversion it was integrated in, but I know it was after ISR12.

    I've got a workaround for ISR12 though. If you add *.PININFO statements within the .SUBCKT, you can force the pins to be input pins. For example:

     * example of block with supplies
    .SUBCKT blockWithSupplies Y A VDD VSS
    *.PININFO VDD:I VSS:I
    MP1 Y A VDD VDD pch w=2u l=0.5u
    MN1 Y A VSS VSS nch w=1u l=0.5u
    .ENDS

    BTW (to answer your last question), this is nothing to do with the Assura version you have installed. Assura doesn't even need to be in your path for SPICEIN to work.

    Regards,

    Andrew.

     

Reply

  • Hi Kevin,

    I just tried it in ISR12, and got:

    WARNING (CONN2SCH-136): The cell view terminal VDD is connected to a global signal VDD. The cell view
    terminal name will be suffixed with !.
    WARNING (CONN2SCH-136): The cell view terminal VSS is connected to a global signal VSS. The cell view
    terminal name will be suffixed with !.
    WARNING (CONN2SCH-134): The signal VDD is a global signal but does not end with '!'.
    WARNING (CONN2SCH-134): The signal VSS is a global signal but does not end with '!'.

    And I see the pins as being VDD! etc. I don't get this in IC615 ISR16. A bit of searching, I found CCR 910263 which implemented this (unfortunately I can't quite see which subversion it was integrated in, but I know it was after ISR12.

    I've got a workaround for ISR12 though. If you add *.PININFO statements within the .SUBCKT, you can force the pins to be input pins. For example:

     * example of block with supplies
    .SUBCKT blockWithSupplies Y A VDD VSS
    *.PININFO VDD:I VSS:I
    MP1 Y A VDD VDD pch w=2u l=0.5u
    MN1 Y A VSS VSS nch w=1u l=0.5u
    .ENDS

    BTW (to answer your last question), this is nothing to do with the Assura version you have installed. Assura doesn't even need to be in your path for SPICEIN to work.

    Regards,

    Andrew.

     

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