I am trying to import a CDL netlist using Spice In to generate a schematic view. However, I would like to keep the VDD and VSS pins local. When the import process calls conn2sch, conn2sch insists on appending a '!' to those net names because it thinks they should be global...
In my CDL netlist, there is no *.GLOBAL or *.PIN control statement, and the subcircuit header reads as
.SUBCKT cell1 Y VDD VSS A
I generated just a netlist view and sure enough the VDD and VSS signals in the view have isGlobal set to 't'. Where does this occur in the translation process, and how can I prevent that from happening?
I'm really glad to hear that what I was seeing was in fact incorrect behaviour! I've been pulling my hair out reading the documentation trying to see where I could've been going wrong.
Thanks for the fix with *.PININFO; is this a result of the .subckt internal *.PININFO declaration forcing those pins to look local?
And about the Assura version, I was aware that it didn't need to be in the path (as it is in fact not in our setup), I was just grasping at straws :).
Thanks again for the help!