cds_generic nmos extracting as 4-terminal

Hi jmoriarty

Actually "cds_generic" is not one of the libraries that can be found in Virtuoso installation. I believe that it has been most likely created by your CAD support. You will need to get their help to resolve the issue. In the meantime, you can try using "nmos" cell from "analogLib" library. Just add the following line in your cds.lib file:

DEFINE analogLib $CDSHOME/tools/dfII/etc/cdslib/artist/analogLib

Best regards
Quek

Thanks very much Quek, and sorry.  I'll wipe the egg off of my face and go postal on my CAD team.

 Jack

Sorry; spoke too quickly.  Exact same problem with analogLib, which is probably from where the local cds_generic library is copied.  I'm afriad that the issue is still open, but it applies to the "nmos" cell in the "analogLib" library.  The spectre view has four terminals and it should have only three, so the the device extracts as a 4-terminal device when the "symbol" view is instantiated.  Just change "cds_lib" to "analogLib" in the original post, and everything else applies.  Sorry for the confusion.

 Jack

Hi Jack

Actually the situation is as follows:

The nmos cell has only 3 terminals but will be netlisted as a usual 4 terminal mos device as requested by bsim model requirements. The 4th terminal (bulk) is hidden because it has been set as an inherited connection in the spectre view. If you open up the properties form of the "B" pin in the spectre view, you will find that the inherited property name is "bulk_n" and the default global net is gnd!.

Inherited connection allows easy overriding of a net from the top level. E.g. if user does not specify the value of bulk_n property, the bulk terminal will be netlisted using the global ground "0". That's why you have "0" as the net name in your netlist.

You can override the default gnd! as follows:
a. Create a new schematic and place an instance of "nmos" from analogLib
b. Open ADE and do spectre netlisting
c. You will get "0" as the bulk net
d. Now open up properties form of the nmos instance
e. Add a "netSet" bulk_n property as shown below and set its value to "abc"
f. Check and save the schematic
g. Re-do netlisting using ADE
h. You will now have (net1 net2 net3 abc) in the netlist and not (net1 net2 net3 0)

Unless your spectre model file specifically uses 3 terminal model instead of 4 terminals, you should not remove the inherited connection in the spectre view. If you would like to specify the terminal net explicitly, you should use "nmos4" cell instead of "nmos" cell.

Hope that this clears up the issue. : )

Best regards
Quek

Thanks very much Quek. Actually, once the cell is copied, it's just as easy to delete the two pins from the spectre view, though I have used the netSet property before in other situations.

The reason that a three-terminal symbol is useful is that models for discrete DMOS devices generally are three-terminal. Having a three-terminal symbol available in a standard spectre library allows the user simply to instantiate the three-terminal symbol and populate the model field with the name of the model provided by the DMOS manufacturer. (It is assumed that the models library has already been added to the user's model path.)   

 I'd like to request that a three terminal symbol be added to analogLib if possible. Cadence could call it "nmos3" to fit with the "nmos" and "nmos4" devices already there. I think it would get used, maybe more than the other two cells because most companies use their own libraries or use libraries from fab PDKs for design, either of which includes symbols compatible with bsim models.  On the other hand, it's easy to create a copy, so not really that important.

Thanks again Quek.

Jack

Jack,

Actually, very few people use the transistor components directly from analogLib for any technology - this is because sometimes you even have 5th terminals - or other variants. Best to have your own components to suit your own needs.

I'm not sure all DMOS devices (especially if on-chip) have 3 terminals either...

You could use nmes, as that has 3 terminals. Not really a MESFET of course, but it may keep things simple.

By all means though, contact customer support if you want the enhancement request.

Kind Regards,

Andrew.

Thanks much Andrew.  The three-terminal models are provided by _discrete_ power DMOS manufacturers.  For example, IR, Vishay Siliconix, and Fairchild all provide three-terminal models, and I would guess that most of the rest do as well.  Of course, the models were intended for use by PCB-level designers who wouldn't be Virtuoso customers, but it is common for _IC_ designers to perform simulations using the external models to better predict how a power controller IC design will perform with actual, commercially available transistors.  Again, not a big deal to copy the analogLib component and edit it, but it just seemed like an opportunity to use the standard library transistor symbols provided by Cadence, for which I have never, ever had a need before.  As I mentioned, most IC designers work from other libraries so I'm guessing that the "nmos" and "nmos4" cells are used by a very small segment of your customer base.  If you provided a three-terminal cell, it might get some use from your power conversion customers, along with any other users whose ICs work with discrete transistors.  Those combined comprise a small, but not insignificant segment of the IC tool market.

 Thanks again Andrew.  Your posts serve as an educational resource to us all.

 Jack

Jack,

I entirely understood that this was for discrete transistors - I was just explaining the most common usage.

As I mentioned, feel free to contact customer support over this enhancement (it's more likely to get done if tied to a customer than if I ask for it - it allows us to tie together similar requests and get a better sense of the demand).

And thanks for using the forums!

Regards,

Andrew