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cds_generic nmos extracting as 4-terminal

jmoriarty

Using IC6.1.5-64b.500.9.  

Instantiating "nmos" (not "nmos4") symbol view from "cds_generic" library in which the model field is populated with "mod".  It extracts as  follows:

M6 (0 0 0 0) mod

The symbol view has only 3 terminals, and there are only 3 terminals in the pin list. There appears to be an error in the "spectre" view, which shows 4 terminals.  Only fix is to copy "symbol" and "spectre" views to an editable library and delete a terminal from the "spectre" view.  If this is indeed an error, can it be corrected in the next release?  If there is already an open ticket I appologize for not finding it.

 Thanks.

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  • jmoriarty

    Thanks much Andrew.  The three-terminal models are provided by _discrete_ power DMOS manufacturers.  For example, IR, Vishay Siliconix, and Fairchild all provide three-terminal models, and I would guess that most of the rest do as well.  Of course, the models were intended for use by PCB-level designers who wouldn't be Virtuoso customers, but it is common for _IC_ designers to perform simulations using the external models to better predict how a power controller IC design will perform with actual, commercially available transistors.  Again, not a big deal to copy the analogLib component and edit it, but it just seemed like an opportunity to use the standard library transistor symbols provided by Cadence, for which I have never, ever had a need before.  As I mentioned, most IC designers work from other libraries so I'm guessing that the "nmos" and "nmos4" cells are used by a very small segment of your customer base.  If you provided a three-terminal cell, it might get some use from your power conversion customers, along with any other users whose ICs work with discrete transistors.  Those combined comprise a small, but not insignificant segment of the IC tool market.

     Thanks again Andrew.  Your posts serve as an educational resource to us all.

     Jack

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  • jmoriarty

    Thanks much Andrew.  The three-terminal models are provided by _discrete_ power DMOS manufacturers.  For example, IR, Vishay Siliconix, and Fairchild all provide three-terminal models, and I would guess that most of the rest do as well.  Of course, the models were intended for use by PCB-level designers who wouldn't be Virtuoso customers, but it is common for _IC_ designers to perform simulations using the external models to better predict how a power controller IC design will perform with actual, commercially available transistors.  Again, not a big deal to copy the analogLib component and edit it, but it just seemed like an opportunity to use the standard library transistor symbols provided by Cadence, for which I have never, ever had a need before.  As I mentioned, most IC designers work from other libraries so I'm guessing that the "nmos" and "nmos4" cells are used by a very small segment of your customer base.  If you provided a three-terminal cell, it might get some use from your power conversion customers, along with any other users whose ICs work with discrete transistors.  Those combined comprise a small, but not insignificant segment of the IC tool market.

     Thanks again Andrew.  Your posts serve as an educational resource to us all.

     Jack

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