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  3. model card vith a verilogA model through spectre

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model card vith a verilogA model through spectre

Fabb
Fabb over 12 years ago

Hello,

I would like to run my own verilogA model with spetcre through a model card approach.

Nevertheless my model paramaters are not recognized, so not took into account in the simulation

#------------------------mymodel.va
module mymodel(T1,T2);
    
    inout T1, T2;
    electrical T1, T2;

    // instance parameters
    parameter real    ip1=1;
    //Technology Parameters
    parameter real tp1=1;
        analog begin
        @(initial_step)
        begin
            $strobe("----> mymodel");
            $display("Instance parameters: ip1=%r, ip1);
            $display("Technology parameters: tp1=%r , tp1);
        end
    endmodule

#------------------------model card
simulator lang=spectre

library test

section means
    parameters efftp1 = 777
        include "model_cards.scs" section=core
endsection means


section core
    ahdl_include "mymodel.va"        
    model device1 mymodel
        +tp1 = efftp1
endsection core
endlibrary

#------------------------cdf parameters
((nil name "ip1" paramType "string" defValue "1" prompt "ip1" choices nil parseAsNumber t units "lengthMetric" use nil display nil editable nil dontSave nil callback nil storeDefault t parseAsCEL t) (nil name "model" paramType "string" defValue "" prompt "model name" choices nil parseAsNumber nil units nil use nil display nil editable nil dontSave nil callback nil storeDefault nil parseAsCEL t))
(nil spectre (nil modelParamExprList "" optParamExprList "" opParamExprList "" stringParameters "" propMapping "" termMapping "nil T1 \\:1 T2 \\:2" termOrder "T1 T2" componentName "" instParameters "radius" otherParameters "model" netlistProcedure "") hspiceD (nil opParamExprList "" optParamExprList "" propMapping "" termMapping "" termOrder "" namePrefix "" componentName "" instParameters "" otherParameters "" netlistProcedure "") auLvs (nil namePrefix "" permuteRule "" propMapping "" deviceTerminals "" termOrder "" componentName "" instParameters "" otherParameters "" netlistProcedure "") auCdl (nil dollarEqualParams "" dollarParams "" modelName "" namePrefix "" propMapping "" termOrder "" componentName "" instParameters "" otherParameters "" netlistProcedure "") ams (nil isPrimitive "" extraTerminals "" propMapping "" termMapping "" termOrder "" componentName "" excludeParameters "" arrayParameters "" stringParameters "" referenceParameters "" enumParameters "" instParameters "" otherParameters "" netlistProcedure ""))
(nil paramLabelSet nil opPointLabelSet nil modelLabelSet nil paramDisplayMode nil paramEvaluate "nil nil nil nil nil" paramSimType nil termDisplayMode nil termSimType nil netNameType nil instDisplayMode nil instNameType nil)
(nil doneProc "" formInitProc "" promptWidth 175 fieldWidth 350 buttonFieldWidth 340 fieldHeight 35)

#------------------------error message

tp1 not recognized in mymodel.va


How should I proceed to allow parameters to be modified in a modelCard.

Regards,

Fabrice

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  • Fabb
    Fabb over 12 years ago
     Andrew,

     

    Thanks a lot, indeed your solution is helping me.

    The two statements

    (* compact_module *)
    (* instance_parameter_list ={ip1} *)

    are probably  mandatories only for spectre, isn't it?

    Secondly, these two statments are not documented neither in varilogA doc or spectre doc, is it normal?

     

    Regards,


    Fabrice

     

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  • Fabb
    Fabb over 12 years ago
     Andrew,

     

    Thanks a lot, indeed your solution is helping me.

    The two statements

    (* compact_module *)
    (* instance_parameter_list ={ip1} *)

    are probably  mandatories only for spectre, isn't it?

    Secondly, these two statments are not documented neither in varilogA doc or spectre doc, is it normal?

     

    Regards,


    Fabrice

     

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