model card vith a verilogA model through spectre

Fabrice,

Other than the syntax errors in your VerilogA module (missing quotation marks, missing  end statement, you also need some attributes to tell it that it is a "compact module" and which parameters are instance (versus model) parameters. So changing it to this:

 `include "disciplines.vams"

(* compact_module *)
(* instance_parameter_list ={ip1} *)
module mymodel(T1,T2);
    
    inout T1, T2;
    electrical T1, T2;

    // instance parameters
    parameter real    ip1=1;
    //Technology Parameters
    parameter real tp1=1;
      analog begin
        @(initial_step)
        begin
            $strobe("----> mymodel");
            $display("Instance parameters: ip1=%r", ip1);
            $display("Technology parameters: tp1=%r" , tp1);
        end
      end
endmodule

Does what you want. Note that there's a typo in the documentation with regards to the instance_parameter_list attribute - it doesn't show the "=" in the documentation. CCR 808807 is to get this fixed.

Regards,

Andrew.

Fabrice,

They are documented in the VerilogA manual (in MMSIM11.1 and MMSIM12.1 at least; I didn't check older releases). I don't know if they are supported in other simulators. Other simulators would also need to know the difference between instance and model parameters, if they support compact device modelling in VerilogA.

Kind Regards,

Andrew.

 indeed i was looking for in an old doc.

thanks again for your help

fab

Hello,

 In my case I am declaring new quantities (nature and discipline) in my veriloga file.

I needed this to boost the value of the blowup in order to avoid some convergence problems I encountered.

Now, I target to set my model card.

using the lines : `include "disciplines.vams"   //(* compact_module *)  (* instance_parameter_list ={a,b} *)  on top of my code, I get tghe following error when I launch my simulations  ""Error found by spectre during AHDL read-in.  ERROR (VACOMP-2259): "nature<<--?  new_current"

Although when I don't use  //(* compact_module *)  (* instance_parameter_list ={a,b} *)  on top of my code and subsequently I use subckt in my .scs file I don't have any error and that works good !

To conclude, can We deduce that I can not use new quantities in my veriloga code if I use  //(* compact_module *)  (* instance_parameter_list ={a,b} *)  on top of my code ?

Thanks in advance

 Best regards 

Kotb 

Hello,

I am defining BSIMCMG verilog-a model in cadence and I created a symbol for it, but I dont know how to attache the model card with this model. As when I run simulation, since the model card is not defined, these missing model parameters  appear as undefined design variables that need to be defined manually.

I would like to know how to define the model card to define these parameters automatically 
The model card is in spice format:

.model nmos1 bsimcmg
+ BULKMOD = 1
+ CAPMOD = 0
+ COREMOD = 0
...

Thanks

First of all, bsimcmg is available as a built-in model in spectre, so using a VerilogA model is going to be less efficient.

You can specify the model card via Setup->Model Libraries in ADE. It's fine if it's in SPICE syntax - just make sure that the file does not have the ".scs" suffix (any other suffix will be assumed to be in SPICE syntax).

If you really do need to use the VerilogA model, you'd have to ensure that the VerilogA module has the correct attributes to ensure that the parameters are recognized as model parameters - but maybe you won't need to do that...

Regards,

Andrew.

Yea, I know that bsimcmg is built-in in spectre, but i need to define the verilog-a.

I defined it before in the model librareis, but still can't be read by the verilog-a, I think that I miss these correct attributes, are there some lines I need to add to the verilog-a file to recognize that model card defined in the model library?

Thanks,

I was searching for where I'd answered this (the attributes needed) before, and realised that you've appended to the same thread where I'd answered it already!

With the attributes in the post, it tells spectre which parameters are instance parameters (and the rest are model parameters) - and having done that you can then specify a model card. You would have to include the veriloga model via a model file too (you can't really have it as a view, because you want the module to be generic and not just for that view). So you'd have your transistor symbol with the CDF set up with all the instance parameters you want to be able to pass to the model, and the spectre simulation information set up to netlist those parameters, and with the model parameter set to "nmos1" or whatever you've called it. You'd have a spectre view (copy of the symbol) to tell it to stop at that point. You could (say) copy from nmos4 in analogLib and then change the CDF parameters to suit your needs (Tools->CDF->Edit and set the CDF type to "Base").

Then you'd have a file which you'd add to your model files - say "myBsimcmg.scs" which contains:

ahdl_include "/path/to/bsimcmg.va"

As well as referencing your model file.

Regards,

Andrew.