I want to include parameters, i.e. module parameters to the schematic. The schematic is 1 level above the ahdl code and the simulator is supposed to simulate it using the ahdl code.However when I include the parameters in the code and use the ahdl parser, it complains that it cannot find the declaration of those parameters anywhere.Is there a way in which we can specify those parameters which the module might be needing in the schematic/symbol itself so that when a new cell ahdl view is generated based on it, the parameters are already included in the code..Hoping to hear from u,Aijaz.
I normally start with the Create New Cellview- (suing Verilog-A editor ) from the library manager.. I set my editor to nedit (www.nedit.org) and use the Verilog-A.pats file you can download from their website.. (or by email to firstname.lastname@example.org) each time you save and exit - the system will do a syntax check, and then, if it passes, it will build the required symbol view for it.. (if you answer yes.. )If you START with a symbol, any parameters you add will be added to the CDF automatically when you "check and save" your veriloga view.. -- BUT THATS not what you are asking.. After that, If I create another view (ie Verilog-AMS) those parameters that exist in the CDF are automatically included in the new verilog-AMS view.. .. So there MUST be a way to do it.. from icfb menu .. Tools -> CDF -> editenter lib and cell nameunder component parameters "Add" -(as first parameter or after (existing) parameter name)set paramtype to "string"parse as number to "yes"units "don't use"parseAsCEL "yes"store default NOthe NAME is the parameter name you get in your verilog-A view (spectreHDL is obsolete now!)the PROMPT is what you'll see when you "q" the instance of this to set the parameter - by default its the same as the NAMEthe defValue is the default value (if set it will be in your verilog-ams verilog-a view when you create a new cell view)the display parameter can be blank, - but the auto created parameters get "artParameterInToolDisplay('name)"any CDF parameter you add this way will be added to your verilog-A or verilog-AMS view.. HTH jbd\
If you define parameters in Verilog-A, their values can be overridden from the symbol on the schematic. The Verilog-A code will not be changed but instead, the schematic value will override the default value in each instantiation line in the netlist.To see this in action, create a new Verilog-A cell and look at the CDF from CIW->Tools->CDF->Edit.Regards,Samir Jafferali