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adding ahdl parameters to schematic

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I want to include parameters, i.e. module parameters to the schematic. The schematic is 1 level above the ahdl code and the simulator is supposed to simulate it using the ahdl code.
However when I include the parameters in the code and use the ahdl parser, it complains that it cannot find the declaration of those parameters anywhere.
Is there a way in which we can specify those parameters which the module might be needing in the schematic/symbol itself so that when a new cell ahdl view is generated based on it, the parameters are already included in the code..

Hoping to hear from u,

Aijaz.


Originally posted in cdnusers.org by aijazbaig1
Parents

  • If you define parameters in Verilog-A, their values can be overridden from the symbol on the schematic. The Verilog-A code will not be changed but instead, the schematic value will override the default value in each instantiation line in the netlist.

    To see this in action, create a new Verilog-A cell and look at the CDF from CIW->Tools->CDF->Edit.

    Regards,

    Samir Jafferali


    Originally posted in cdnusers.org by AMSamirj
Reply

  • If you define parameters in Verilog-A, their values can be overridden from the symbol on the schematic. The Verilog-A code will not be changed but instead, the schematic value will override the default value in each instantiation line in the netlist.

    To see this in action, create a new Verilog-A cell and look at the CDF from CIW->Tools->CDF->Edit.

    Regards,

    Samir Jafferali


    Originally posted in cdnusers.org by AMSamirj
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