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Error in verilogA

sreeni

Hi to all

Am designing one model in verilog-A. 

In that i have defined one function (Charge_low) and while using it in the main design it showing some error.

Am not able to understand the error.

 hsp-vacomp: Error: syntax error

 hsp-vacomp:     ['SBCNTFET.va',399]

 hsp-vacomp:     Qs_low1 = Charge_low(  2.32  ,H1,b1_1,b0_1)-Charge_low(`alpha_1,L1,b1_1,b0_1);
 hsp-vacomp:                                                         ^

 Error was showing @ the "," after H1.

All variables in the function are declared as real and defined.

Please let me know what may be the error.

 

Thanks

SRINI

 

Parents

  •  Hi Andrew,

    What ever you mentioned 1 and 2 were the errors. And now its bug free.

    Thank you so much

     When it showing error in one line i was thinking of same line not the actual function.

    Once again thanks 

     Regards

    SRINI

Reply

  •  Hi Andrew,

    What ever you mentioned 1 and 2 were the errors. And now its bug free.

    Thank you so much

     When it showing error in one line i was thinking of same line not the actual function.

    Once again thanks 

     Regards

    SRINI

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