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Need workaround for duplicate veriloga module name issue

JKupanna

Hi,

For some reason I'm including the same model file twice in a spectre simulation. In that .scs file I have a ahdl_include statement that includes a varilog-a model. Now because I'm loading this file twice, It is throwing an error saying that

"A built-in or regular master with name xyz already exists, cannot create an alias master with same name"

 Is there a option similar to duplicate_subckt=warning for verilog-a model.

 Thanks,

Jagadish 

  

Parents

  • Thanks for your response Andrew.

    I'm using Spectre 11.1.0.581.isr18. I don't have the latest ISR installed at my end to try duplicate_module option.

    Actually, I'm running Spectre with +mts option. My setup looks something like this,

    input.scs

    -----------------------------------------

    include "a.scs"

    subckt A

    include "a.scs"

    ends A

    subckt B

    include "b.scs"

    ends B

    -----------------------------------------

    With this kind of setup, I'm getting the below error,

    ERROR (SFE-398): "/path/resistors.va 91: A built-in or regular master with name rf_va already exists, cannot create an alias master with the same name."

    If I comment the first line(ie: provide models at scope level) then the simulation runs fine. Well I can go ahead and keep the a.scs as global model and comment the scope level model and run the simulation. But I was wondering if there is a way to workaround the current error.

    Regards, Jagadish

Reply

  • Thanks for your response Andrew.

    I'm using Spectre 11.1.0.581.isr18. I don't have the latest ISR installed at my end to try duplicate_module option.

    Actually, I'm running Spectre with +mts option. My setup looks something like this,

    input.scs

    -----------------------------------------

    include "a.scs"

    subckt A

    include "a.scs"

    ends A

    subckt B

    include "b.scs"

    ends B

    -----------------------------------------

    With this kind of setup, I'm getting the below error,

    ERROR (SFE-398): "/path/resistors.va 91: A built-in or regular master with name rf_va already exists, cannot create an alias master with the same name."

    If I comment the first line(ie: provide models at scope level) then the simulation runs fine. Well I can go ahead and keep the a.scs as global model and comment the scope level model and run the simulation. But I was wondering if there is a way to workaround the current error.

    Regards, Jagadish

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