Stats

  • Locked Locked
  • Replies 4
  • Subscribers 125
  • Views 16811
  • Members are here 0
This discussion has been locked.
You can no longer post new replies to this discussion. If you have a question you can start a new discussion

schematic editor question: tie two global signals together

apple419

Hi, cadence virtuoso schematic editor L (615) users:

   How to tie two global signals together so that when netlist there is only one global signal name for both cases.

   For example, in my design all digital parts have ground vss! and all analog parts have ground vssa!. Since the design only has one ground pin VSS, I need to tie vss! and vssa! together to the pin VSS. This way I will not have ant LVS problem.

   I tried to do this (put symbol vss and symbol vssa on the schematic page and tie them together to the pin VSS),

   but after check and save, Cadence gave errors:

   Error: Net "vss!" shorted to net "vssa!",

   Error: Global signal "vss!" shorted to terminal "VSS".

   Does anyone have similar issues? It looks like two global nets can not be tied together. Is it right?

 

Thanks!! 

 

  • You cannot create a net alias between two pins, a pin and a global, or two globals. You can create them between two internal nets, a pin and an internal net or a global and an internal net (e.g. using the "patch" component from the basic library).

    You could create a "virtual" short using the cds_thru component from basic.

    Regards,

    Andrew.

  • Hi Andrew,

        Thanks for your reply. I tried with the cds_thru method. I noticed it created iprobe comonents in the spectre netlist. Not sure if it works with LVS.

       By the way, we use Mentor Caliber for LVS. What type of netlist can Caliber take? Can it take spectre netlist? Spectre netlist may not work since it is mainly for simulation... 

    Regards

     

  •  Calibre will use a CDL netlist (a SPICE-like format that originated with Dracula), available via File->Export->CDL. Depending on the version you're using, the cds_thru will be netlisted as either a small valued resistor (which can be filtered by Calibre by ensuring the *.RESI construct is in the netlist with a threshold above the value that the cds_thru is netlisted as), or as an attempt to short the nets in the auCdl netlister, or by netlisting it as a .CONNECT statement which is CDL-speak for a short.

    The cds_thru uses different approaches in different netlisters to represent the short - using something appropriate in each language.

    Regards,

    Andrew.

  • Andrew,

        Thanks! This is very helpful. I may have more questions when I am at the stage to do LVS...

     Best regards

    Apple 

     

Community Guidelines

The Cadence Design Communities support Cadence users and technologists interacting to exchange ideas, news, technical information, and best practices to solve problems and get the most from Cadence technology. The community is open to everyone, and to provide the most value, we require participants to follow our Community Guidelines that facilitate a quality exchange of ideas and information. By accessing, contributing, using or downloading any materials from the site, you agree to be bound by the full Community Guidelines.