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Long term jitter from SpectreRF's Phase noise?

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Hi,
 
It is true that we can get Jitter from Phase noise simulated from the Spectre by integrating over a noise band of interest. It evident that from the tool that we can get Jcc(cycle to Cycle Jitter) and Jee(Edge to Edge) and Jc.

But I want to know wether we can get "long term jitter" from the SpectreRF's Phase noise simulation.  kindly tell me wether we have any other ways to measure the long term jitter from the spectre.

I beleive the eyediagram technique with transient analysis will not include random noise and other noises.

Also in the Direct plot menu after Pnoise analysis. we have the term "K"( no of cycles). Can you pls tell me what is it.

Can we set k=3000 or (like that number ) to het the longterm jitter?

kindly reply.

Thanks & regards
SavithRu


Originally posted in cdnusers.org by savithru
Parents

  • I can't tell whether 10kHz is low enough in frequency from the information you've given. If you want 3000 cycles, you need to go down as low as Fcycle/3000 - so if your clock is above 30MHz, you'll be OK.

    Since the jitter is coming from the noise analysis that is done, there is no need to simulate more cycles in the time domain. A single cycle of the output clock will be enough to capture the non-linearities so that pnoise can include all the noise folding that occurs in the circuit. It can then compute the noise response over frequency, and the k-cycle jitter will be dependent on integrating over that number of cycles (but in the frequency domain). So provided you have simulated the pnoise low enough in frequency to capture the noise at that fraction of your clock frequency, you'll be OK. The integration itself is far from trivial, but the pnoise form takes care of that - you just need to ensure that the frequency range is wide enough, and that it you've asked for the number of cycles you want.

    The result should be realistic (in terms of the the random jitter). You won't of course be capturing any deterministic jitter this way.

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
Reply

  • I can't tell whether 10kHz is low enough in frequency from the information you've given. If you want 3000 cycles, you need to go down as low as Fcycle/3000 - so if your clock is above 30MHz, you'll be OK.

    Since the jitter is coming from the noise analysis that is done, there is no need to simulate more cycles in the time domain. A single cycle of the output clock will be enough to capture the non-linearities so that pnoise can include all the noise folding that occurs in the circuit. It can then compute the noise response over frequency, and the k-cycle jitter will be dependent on integrating over that number of cycles (but in the frequency domain). So provided you have simulated the pnoise low enough in frequency to capture the noise at that fraction of your clock frequency, you'll be OK. The integration itself is far from trivial, but the pnoise form takes care of that - you just need to ensure that the frequency range is wide enough, and that it you've asked for the number of cycles you want.

    The result should be realistic (in terms of the the random jitter). You won't of course be capturing any deterministic jitter this way.

    Regards,

    Andrew.


    Originally posted in cdnusers.org by adbeckett
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