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Verilog design in Cadence

kenambo

 Hi,

 Is there anyway that i can design a digital circuit in Virtuoso Schematic window...

And include the *.v file in the schematic capture window..

 

Thanks...

Parents

  • Yes. You can create textual Verilog views (File->New->CellView and set the Type to "Verilog" - give the lib/cell/view a name). Then in the resulting editor create the Verilog representation. When you save and exit the editor, it will syntax check the view and then prompt you to create a symbol. You can instantiate this in the schematic.

    Regards,

    Andrew.

     

Reply

  • Yes. You can create textual Verilog views (File->New->CellView and set the Type to "Verilog" - give the lib/cell/view a name). Then in the resulting editor create the Verilog representation. When you save and exit the editor, it will syntax check the view and then prompt you to create a symbol. You can instantiate this in the schematic.

    Regards,

    Andrew.

     

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