Verilog design in Cadence

Yes. You can create textual Verilog views (File->New->CellView and set the Type to "Verilog" - give the lib/cell/view a name). Then in the resulting editor create the Verilog representation. When you save and exit the editor, it will syntax check the view and then prompt you to create a symbol. You can instantiate this in the schematic.

Regards,

Andrew.

 Hi all,

I'm trying to build a voltage controlled curent source,I opened a new file with a verilogAMS text and write the following:

module VCCS(p,n,pc,nc);
inout p,n;
input pc,nc;
electrical p,n,pc,nc;
parameter real gain=1;
branch (p,n) iSrc;
analog begin
I(iSrc) <+ gain*V(pc,nc);
end
endmodulet pc,nc;

and I created a symbol for it then I instantiate it on the schematic page but the output is always zero?

Can any one help me?

thanks

 Thanks.. so i have to write a .v file and create a symbol.. am i right...

What is the difference between this and the synthesis tool

Thanks,,....

Sali said:

module VCCS(p,n,pc,nc);
inout p,n;
electrical p,n,pc,nc;
parameter real gain=1;
branch (p,n) iSrc;
analog begin
I(iSrc) <+ gain*V(pc,nc);
end
endmodulet pc,nc;

Not sure why you posted this on the end of another thread, but the code you posted has typos in it - it wouldn't even syntax compile. I used a command-line example to try this out (having fixed the typos):

`include "disciplines.vams"

module VCCS(p,n,pc,nc);
inout p,n;
input pc,nc;
electrical p,n,pc,nc;
parameter real gain=1;
branch (p,n) iSrc;
analog begin
I(iSrc) <+gain*V(pc,nc);
end
endmodule

module test;
electrical gnda;
ground gnda;

vsource #(.freq(1M),.ampl(0.5), .type("sine")) V1(n1,gnda);
resistor #(.r(1k)) R1(op1,gnda);
VCCS #(.gain(1m)) I1(op1,gnda,n1,gnda);

endmodule

And this together with testVCCS.scs :

tran tran stop=2u

I then ran "irun -gui testVCCS.scs testVCCS.vams" and I see these results (having problems uploading the picture, so I'll try again in a moment). Looks pretty OK to me.

Andrew.

kenambo said:

 Thanks.. so i have to write a .v file and create a symbol.. am i right...

What is the difference between this and the synthesis tool

A synthesis tool takes RTL (Register Transfer Level) code and converts it into a gate level representation. Writing a Verilog text view and simulating that just means that you're simulating what you wrote without it being synthesized. So it's a bit like asking what is the difference between an orange and a car - two completely different things.

Regards,

Andrew.